Display panel and display apparatus

ABSTRACT

A display panel includes a substrate including a display area and a peripheral area around the display area, the display area including a front display area, a corner display area extending from a corner of the front display area, and a middle display area between the front display area and the corner display area, a pixel arranged on the front display area and including a display element, a gate driving circuit arranged on a side of the peripheral area, a data driving circuit arranged on the side on which the gate driving circuit is arranged, a gate line connected to the gate driving circuit and extending to be connected to the pixel, and a data line connected to the data driving circuit and extending to be connected to the pixel.

This application claims priority to Korean Patent Application No.10-2020-0111291, filed on Sep. 1, 2020, and all the benefits accruingtherefrom under 35 U.S.C. § 119, the content of which in its entirety isherein incorporated by reference.

BACKGROUND 1. Field

One or more embodiments relate to a display panel and a displayapparatus in which a display area for displaying images is expanded.

2. Description of the Related Art

Electronic devices based on mobility have come into widespread use.Recently, tablet personal computers (“PCs”), in addition to small-sizedelectronic devices such as mobile phones, are widely being used asmobile electronic devices.

In order to support various functions, for example, to provide a userwith visual information such as images or videos, the mobile electronicdevices include a display apparatus. Recently, as components for drivingsuch display apparatuses have become miniaturized, occupancy of thedisplay apparatuses in electronic devices is gradually increasing.Moreover, a structure that may be curved to have a predetermined anglefrom a flat state has been developed.

A display panel for displaying an image, which is included in a displayapparatus, includes various curvatures, such as a front display area, afirst side display area extending from the front display area in a firstdirection and bent, and a second side display area extending from thefront display area in a second direction and bent, for example.

SUMMARY

One or more embodiments include a display panel and a display apparatusincluding a bendable corner display area arranged to correspond to thecorner of a front display area.

Additional embodiments will be set forth in part in the descriptionwhich follows and, in part, will be apparent from the description, ormay be learned by practice of the presented embodiments of theinvention.

A display panel in an embodiment includes a substrate including adisplay area and a peripheral area around the display area, the displayarea including a front display area, a corner display area extendingfrom a corner of the front display area, and a middle display areabetween the front display area and the corner display area, a pixelarranged on the front display area and including a display element, agate driving circuit arranged on a side of the peripheral area, a datadriving circuit arranged on the side on which the gate driving circuitis arranged, a gate line connected to the gate driving circuit andextending in a first direction to be connected to the pixel, and a dataline connected to the data driving circuit and extending in a seconddirection intersecting the first direction to be connected to the pixel.

In an embodiment, the display panel may further include a gateconnection line extending in the second direction and including a firstside connected to the gate driving circuit and a second side connectedto the gate line.

In an embodiment, the display panel may further include a dataconnection line including a first side connected to the data drivingcircuit and a second side connected to the data line adjacent to theedge of the front display area.

In an embodiment, the data connection line may at least partiallyoverlap the front display area.

In an embodiment, the display panel may further include a voltage wirearranged on the substrate to correspond to the middle display area, amiddle display element arranged to at least partially overlap thevoltage wire, and a middle pixel circuit which is connected to themiddle display element and drives the middle display element. The middlepixel circuit may be arranged in the front display area.

In an embodiment, the light-emission area of the display element may besmaller than the light-emission area of the middle display element.

In an embodiment, the display panel may further include a corner displayelement arranged on the substrate to correspond to the corner displayarea, and a corner pixel circuit which is connected to the cornerdisplay element and drives the corner display element. The corner pixelcircuit may be arranged in the front display area or the corner displayarea.

In an embodiment, the light-emission area of the display element may besmaller than the light-emission area of the corner display element.

In an embodiment, the display panel may further include a first cornerwire arranged in the corner display area and connected to the data line,and a second corner wire arranged in the corner display area andconnected to the gate line. The first corner wire and the second cornerwire may be connected to the corner pixel circuit.

In an embodiment, the substrate corresponding to the corner display areamay include a plurality of strip portions each extending in a directionaway from the front display area, and a plurality of spaces each definedbetween adjacent strip portions from among the plurality of stripportions, and penetrating through the substrate. The first corner wireand the second corner wire may be arranged in each of the plurality ofstrip portions.

In an embodiment, the data connection line may at least partiallyoverlap the middle display area.

In an embodiment, the display panel may further include a middle displayelement arranged to at least partially overlap the data connection line,and a middle pixel circuit which is connected to the middle displayelement and drives the middle display element. The middle pixel circuitmay be arranged in the front display area.

In an embodiment, the display panel may further include a corner displayelement arranged on the substrate to correspond to the corner displayarea, and a corner pixel circuit which is connected to the cornerdisplay element and drives the corner display element. The corner pixelcircuit may be arranged in the front display area or the corner displayarea.

In an embodiment, the display panel may further include a first voltagewire and a second voltage wire arranged in the peripheral area andspaced apart from each other with the middle display area between thefirst voltage wire and the second voltage wire, and a voltage connectionline arranged in the corner display area and connecting the firstvoltage wire to the second voltage wire.

In an embodiment, the substrate corresponding to the corner display areamay include a plurality of strip portions each extending in a directionaway from the front display area, and a plurality of spaces each definedbetween adjacent strip portions from among the plurality of stripportions, and penetrating through the substrate. The voltage connectionline may be arranged along the edges of the plurality of strip portions.

In an embodiment, the display panel may further include a corner displayelement arranged on the substrate to correspond to the corner displayarea, and a corner pixel circuit which is connected to the cornerdisplay element and drives the corner display element. The corner pixelcircuit may be arranged in the front display area or the corner displayarea.

In an embodiment, the display panel may further include a middle displayelement arranged on the substrate to correspond to the middle displayarea, and a middle pixel circuit which is connected to the middledisplay element and drives the middle display element. The middle pixelcircuit may be arranged in the front display area or the middle displayarea.

A display apparatus in an embodiment includes a display panel and awindow covering the display panel. The display panel includes asubstrate including a display area and a peripheral area around thedisplay area, the display area including a front display area, a cornerdisplay area extending from a corner of the front display area and bentwith a preset radius of curvature, and a middle display area between thefront display area and the corner display area, a pixel arranged on thefront display area and including a display element, a gate drivingcircuit arranged on a side of the peripheral area, a data drivingcircuit arranged on the side on which the gate driving circuit isarranged, a gate line connected to the gate driving circuit andextending in a first direction to be connected to the pixel, and a dataline connected to the data driving circuit and extending in a seconddirection intersecting the first direction to be connected to the pixel.

In an embodiment, the display panel may further include a gateconnection line extending in the second direction and including a firstside connected to the gate driving circuit and a second side connectedto the gate line, and a data connection line including one sideconnected to the data driving circuit and a second side connected to thedata line. The data connection line may at least partially overlap thefront display area or the middle display area.

In an embodiment, the display panel may further include a voltage wirearranged on the substrate to correspond to the middle display area; amiddle display element arranged to at least partially overlap thevoltage wire, and a middle pixel circuit which is connected to themiddle display element and drives the middle display element. The middlepixel circuit may be arranged in the front display area.

In an embodiment, the display panel may further include a corner displayelement arranged on the substrate to correspond to the corner displayarea, and a corner pixel circuit which is connected to the cornerdisplay element and drives the corner display element. The corner pixelcircuit may be arranged in the front display area or the corner displayarea.

Other embodiments, features, and advantages other than those describedabove will become apparent from the detailed contents, claims anddrawings for carrying out the following invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other embodiments, features, and advantages of certainembodiments of the invention will be more apparent from the followingdescription taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 is a schematic perspective view of an embodiment of a displayapparatus;

FIGS. 2A, 2B, and 2C are schematic cross-sectional views of anembodiment of a display apparatus;

FIG. 3AA is a schematic plan view of an embodiment of a display panel,and FIG. 3AB is an enlarged view of a portion AA indicated by a dot-dashline of the display panel of FIG. 3AA;

FIG. 3B is a magnified plan view of a portion of FIG. 3AA;

FIG. 3C is a magnified plan view of a portion of FIG. 3AA;

FIG. 3DA illustrates cross-sectional views of a data line of FIG. 3B anda pixel circuit of FIG. 3C taken along lines I-I′ and respectively, andFIG. 3DB is an enlarged view of a portion BB indicated by a dot-dashline of FIG. 3DA;

FIG. 4A is a schematic plan view of an embodiment of a display panel,and FIG. 4B is an enlarged view of a portion CC indicated by a dot-dashline of the display panel of FIG. 4A;

FIGS. 5AA and SBA are schematic plan views of an embodiment of amagnified portion of a display panel, and FIGS. 5AB and 5BB are enlargedviews of portions DD and EE indicated by dot-dash lines of FIGS. 5AA andSBA, respectively;

FIGS. 6 and 7 are equivalent circuit diagrams of an embodiment of apixel circuit applicable to a display panel;

FIG. 8A is a magnified plan view schematically illustrating anembodiment of a corner portion;

FIG. 8B is a magnified plan view schematically illustrating anotherembodiment of a corner portion;

FIG. 9 is a magnified plan view schematically illustrating anotherembodiment of a corner portion;

FIG. 10 is a magnified plan view schematically illustrating anotherembodiment of a corner portion;

FIG. 11AA is a schematic plan view of an embodiment of a layout of pixelcircuits and display elements of a display panel, and FIG. 11AB is anenlarged view of a portion FF indicated by a dot-dash line of FIG. 11AA;

FIG. 11B is a cross-sectional view of a bridge wire of FIG. 11AA takenalong line III-III′;

FIG. 11C is a cross-sectional view of a front display area, a middledisplay area, and a corner display area of FIG. 11AA taken along linesIV-IV' and V-V′;

FIG. 11D is a cross-sectional view of a front display area and a middledisplay area of FIG. 11AA taken along lines VI-VI' and VII-VII';

FIG. 12A is a schematic plan view of another embodiment of a layout ofpixel circuits and display elements of a display panel;

FIG. 12B is a schematic plan view of another embodiment of a magnifiedportion of a display panel;

FIGS. 12C and 12D are schematic plan views of an embodiment of a cornerdisplay area; and

FIG. 12E is a cross-sectional view of a pixel circuit of FIG. 12C takenalong line VIII-VIII′.

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments, examples of whichare illustrated in the accompanying drawings, where like referencenumerals refer to like elements throughout. In this regard, theembodiments may have different forms and should not be construed asbeing limited to the descriptions set forth herein. Accordingly, theembodiments are merely described below, by referring to the drawingfigures, to explain embodiments of the description. As used herein, theterm “and/or” includes any and all combinations of one or more of theassociated listed items. Throughout the disclosure, the expression “atleast one of a, b or c” indicates only a, only b, only c, both a and b,both a and c, both b and c, all of a, b, and c, or variations thereof

As the disclosure allows for various changes and numerous embodiments,particular embodiments will be illustrated in the drawings and describedin detail in the written description. Hereinafter, effects and featuresof the disclosure and a method for accomplishing them will be describedmore fully with reference to the accompanying drawings, in whichembodiments of the disclosure are shown. This disclosure may, however,be embodied in many different forms and should not be construed aslimited to the embodiments set forth herein.

One or more embodiments of the disclosure will be described below inmore detail with reference to the accompanying drawings. Thosecomponents that are the same or are in correspondence with each otherare rendered the same reference numeral regardless of the figure number,and redundant explanations are omitted.

It will be understood that although the terms “first”, “second”, etc.may be used herein to describe various components, these componentsshould not be limited by these terms. These components are only used todistinguish one component from another.

As used herein, the singular forms “a”, “an”, and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise.

It will be further understood that the terms “comprises” and/or“comprising” used herein specify the presence of stated features orcomponents, but do not preclude the presence or addition of one or moreother features or components.

It will be understood that when a layer, region, or component isreferred to as being “formed on” another layer, region, or component, itcan be directly or indirectly formed on the other layer, region, orcomponent. That is, for example, intervening layers, regions, orcomponents may be present.

Sizes of elements in the drawings may be exaggerated for convenience ofexplanation. In other words, since sizes and thicknesses of componentsin the drawings are arbitrarily illustrated for convenience ofexplanation, the following embodiments are not limited thereto.

When a certain embodiment may be implemented differently, a specificprocess order may be performed differently from the described order. Forexample, two consecutively described processes may be performedsubstantially at the same time or performed in an order opposite to thedescribed order.

In the specification, “A and/or B” represents A or B, or A and B. Theexpression “at least one of A and B” indicates only A, only B, both Aand B, or variations thereof

It will also be understood that when a layer, region, or component isreferred to as being “connected” or “coupled” to another layer, region,or component, it can be directly connected or coupled to the otherlayer, region, or/and component or intervening layers, regions, orcomponents may be present. For example, when a layer, region, orcomponent is referred to as being “electrically connected” or“electrically coupled” to another layer, region, or component, it can bedirectly electrically connected or coupled to the other layer, region,and/or component or intervening layers, regions, or components may bepresent.

In the following examples, the x-axis, the y-axis and the z-axis are notlimited to three axes of the rectangular coordinate system, and may beinterpreted in a broader sense. For example, the x-axis, the y-axis, andthe z-axis may be perpendicular to one another, or may representdifferent directions that are not perpendicular to one another.

FIG. 1 is a schematic perspective view of an embodiment of a displayapparatus 1, and FIGS. 2A, 2B and 2C are schematic cross-sectional viewsof an embodiment of the display apparatus 1. In detail, FIG. 2Aillustrates a cross-section of the display apparatus 1 taken in a ydirection of FIG. 1. FIG. 2B illustrates a cross-section of the displayapparatus 1 taken in an x direction of FIG. 1. FIG. 2C illustrates across-section of the display apparatus 1 including corner display areasCDA arranged on both sides of a front display area FDA.

Referring to FIG. 1, the display apparatus 1 displays a moving pictureor a still image, and thus may be used as the display screens of variousproducts such as not only portable electronic apparatuses, such asmobile phones, smartphones, tablet personal computers (“PCs”), mobilecommunication terminals, electronic notebooks, electronic books,portable multimedia players (“PMPs”), navigation devices, and ultramobile PCs (“UMPCs”) but also televisions, notebooks, monitors,advertisement panels, and Internet of things (“IOT”) devices.

The display apparatus 1 may also be used in wearable devices such assmart watches, watch phones, glasses-type displays, and head mounteddisplays (“HMDs”). The display apparatus 1 may also be used asdashboards of automobiles, center information displays (“CIDs”) of thecenter fasciae or dashboards of automobiles, room mirror displays thatreplace the side mirrors of automobiles, and displays arranged on therear sides of front seats to serve as entertainment devices for backseat passengers of automobiles.

The display apparatus 1 may have longer edges in a first direction andshorter edges in a second direction. The first direction and the seconddirection may intersect with each other. In an embodiment, the firstdirection and the second direction may define an acute angle, forexample. In another embodiment, the first direction and the seconddirection may form an obtuse angle or a right angle. A case where thefirst direction (for example, the y direction) and the second direction(for example, the x direction) form a right angle will now be focused onand described in detail.

In another embodiment, the length of an edge of the display apparatus 1in the first direction (for example, they direction) may be equal tothat of an edge of the display apparatus 1 in the second direction (forexample, the x direction). In another embodiment, the display apparatus1 may have shorter edges in the first direction (for example, the ydirection) and longer edges in the second direction (for example, the xdirection).

Corners between the longer edges in the first direction (y direction)and the shorter edges in the second direction (x direction) may berounded to have a predetermined curvature.

Referring to FIGS. 2A through 2C, the display apparatus 1 may include adisplay panel 10 and a cover window CW. The cover window CW may functionto protect the display panel 10.

The cover window CW may be a flexible window. The cover window CW mayprotect the display panel 10 while being easily bent along an externalforce without generating cracks and the like. The cover window CW mayinclude glass, sapphire or plastic. In an embodiment, the cover windowCW may be tempered glass (e.g., ultra thin glass (“UTG”)) or colorlesspolyimide (“CPI”), for example. In an embodiment, the cover window CWmay have a structure in which a flexible polymer layer is arranged onone surface of a glass substrate, or may only include a polymer layer.

The display panel 10 may be below the cover window CW. Although notshown in FIGS. 2A through 2C, the display panel 10 may be attached tothe cover window CW by a transparent adhesion member such as anoptically clear adhesive (“OCA”) film.

The display panel 10 may include a display area DA where an image isdisplayed, and a peripheral area PA surrounding the display area DA. Thedisplay area DA may include a plurality of pixels PX, and may display animage through the plurality of pixels PX. Each of the plurality ofpixels PX may include subpixels. In an embodiment, each of the pluralityof pixels PX may include a red subpixel, a green subpixel, and a bluesubpixel, for example. In an alternative embodiment, each of theplurality of pixels PX may include red, green, blue, and whitesubpixels.

The display area DA may include a front display area FDA, a side displayarea SDA, a corner display area CDA, and a middle display area MDA. Eachof the front display area FDA, the side display area SDA, the cornerdisplay area CDA, and the middle display area MDA may include aplurality of pixels PX, and the plurality of pixels PX may display animage.

In an embodiment, the plurality of pixels PX included in each of thefront display area FDA, the side display area SDA, the corner displayarea CDA, and the middle display area MDA may provide an independentimage, for example. In another embodiment, the plurality of pixels PXincluded in each of the front display area FDA, the side display areaSDA, the corner display area CDA, and the middle display area MDA mayprovide portions of one image, respectively.

The front display area FDA may be a flat display area, and may includefirst pixels PX1 each including a display element. The front displayarea FDA may provide a most part of an image.

Pixels PX each including a display element may be also arranged in theside display area SDA. The side display area SDA may display an image bythe pixels PX. The side display area SDA may include a first sidedisplay area SDA1, a second side display area SDA2, a third side displayarea SDA3, and a fourth side display area SDA4. At least one of thefirst side display area SDA1, the second side display area SDA2, thethird side display area SDA3, and the fourth side display area SDA4 maybe omitted.

The first side display area SDA1 and the third side display area SDA3may be connected to the front display area FDA in the first direction(for example, the y direction). In an embodiment, the first side displayarea SDA1 may extend from the front display area FDA in a −y direction,and the third side display area SDA3 may extend from the front displayarea FDA in a +y direction, for example.

The first side display area SDA1 and the third side display area SDA3may have arbitrary radii of curvature and may be bent. In an embodiment,the first side display area SDA1 and the third side display area SDA3may have different radii of curvature, for example. In anotherembodiment, the first side display area SDA1 and the third side displayarea SDA3 may have the same radii of curvature. A case where each of thefirst side display area SDA1 and the third side display area SDA3 hasthe same radius of curvature, namely, a first radius of curvature R1,will now be described in detail. Because the first side display areaSDA1 and the third side display area SDA3 are the same as or similar toeach other, the first side display area SDA1 will now be focused on anddescribed in detail.

The second side display area SDA2 and the fourth side display area SDA4may be connected to the front display area FDA in the second direction(for example, the x direction). In an embodiment, the second sidedisplay area SDA2 may extend from the front display area FDA in a −xdirection, and the fourth side display area SDA4 may extend from thefront display area FDA in a +x direction, for example.

The second side display area SDA2 and the fourth side display area SDA4may have arbitrary radii of curvature and may be bent. In an embodiment,the second side display area SDA2 and the fourth side display area SDA4may have different radii of curvature, for example. In anotherembodiment, the second side display area SDA2 and the fourth sidedisplay area SDA4 may have the same radii of curvature. A case whereeach of the second side display area SDA2 and the fourth side displayarea SDA4 has the same radius of curvature, namely, a second radius ofcurvature R2, will now be focused on and described in detail. Becausethe second side display area SDA2 and the fourth side display area SDA4are the same as or similar to each other, the second side display areaSDA2 will now be focused on and described in detail.

In an embodiment, the first radius of curvature R1 of the first sidedisplay area SDA1 may be different from the second radius of curvatureR2 of the second side display area SDA2. In an embodiment, the firstradius of curvature R1 may be less than the second radius of curvatureR2, for example. In another embodiment, the first radius of curvature R1may be greater than the second radius of curvature R2.

In another embodiment, the first radius of curvature R1 of the firstside display area SDA1 may be the same as the second radius of curvatureR2 of the second side display area SDA2. A case where the first radiusof curvature R1 is greater than the second radius of curvature R2 willnow be focused on and described in detail.

The corner display areas CDA may extend from the corners of the frontdisplay area FDA and may be bent. The corner display areas CDA may bearranged to correspond to corner portions CP. The corner portions CP maybe the corners of the display area DA, and thus may portions of thedisplay area DA where the longer edges of the display area DA in thefirst direction (for example, the y direction) and the shorter edgesthereof in the second direction (for example, the x direction) meet eachother.

The corner display areas CDA may be between adjacent side display areasSDA. In an embodiment, a corner display area CDA may be between thefirst side display area SDA1 and the second side display area SDA2, forexample. A corner display area CDA may be between the second sidedisplay area SDA2 and the third side display area SDA3, between thethird side display area SDA3 and the fourth side display area SDA4, orbetween the fourth side display area SDA4 and the first side displayarea SDA1. Accordingly, the side display area SDA and the corner displayareas CDA may be arranged to surround the front display area FDA, andmay each have an arbitrary radius of curvature and may be bent.

Second pixels PX2 each including a display element may be arranged ineach corner display area CDA. The corner display area CDA may display animage by the second pixels PX2. As will be described later withreference to FIG. 11AA, pixel circuits electrically connected to thesecond pixels PX2 arranged in the corner display area CDA may bearranged in the corner display area CDA, the front display area FDA, orthe side display area SDA. The second pixels PX2 may be electricallyconnected to the pixel circuits arranged in the corner display area CDA,the front display area FDA, or the side display area SDA and may bedriven.

A third radius of curvature R3 of the corner display area CDA may vary.In an embodiment, when the first radius of curvature R1 of the firstside display area SDA1 is different from the second radius of curvatureR2 of the second side display area SDA2, the third radius of curvatureR3 of the corner display area CDA may gradually change within a rangebetween the first radius of curvature R1 and the second radius ofcurvature R2, for example.

In an embodiment, the first radius of curvature R1 of the first sidedisplay area SDA1 is greater than the second radius of curvature R2 ofthe second side display area SDA2, the third radius of curvature R3 ofthe corner display area CDA may gradually decrease in a direction fromthe first side display area SDA1 to the second side display area SDA2.In an embodiment, the third radius of curvature R3 of the corner displayarea CDA may be less than the first radius of curvature R1 and may begreater than the second radius of curvature R2, for example.

In an embodiment, the display panel 10 may further include a middledisplay area MDA. The middle display area MDA may be between the cornerdisplay area CDA and the front display area FDA. In an embodiment, themiddle display area MDA may extend between the side display area SDA andthe corner display area CDA. In an embodiment, the middle display areaMDA may extend between the first side display area SDA1 and the cornerdisplay area CDA, for example. The middle display area MDA may alsoextend between the second side display area SDA2 and the corner displayarea CDA. In an embodiment, the middle display area MDA may be bent.

The middle display area MDA may include third pixels PX3 each includinga middle display element. Voltage wires for providing a voltage may bearranged on the middle display area MDA, and the third pixels PX3 mayoverlap the voltage wires. In this case, the third pixels PX3 may beover the voltage wires. As will be described later with reference toFIG. 11AA, pixel circuits electrically connected to the third pixels PX3arranged in the middle display area MDA may not be arranged in themiddle display area MDA but may be arranged in the front display areaFDA and/or the side display area SDA. The third pixels PX3 may beelectrically connected to the pixel circuits arranged in the frontdisplay area FDA and/or the side display area SDA and may be driven.

In the illustrated embodiment, the display apparatus 1 may display animage not only in the front display area FDA but also in the sidedisplay area SDA, the corner display area CDA, and the middle displayarea MDA. Accordingly, occupancy of the display area DA in the displayapparatus 1 may increase. Because the display apparatus 1 is bent at itscorners and includes the corner display areas CDA displaying an image,an aesthetic sense may improve.

FIGS. 3AA, AB, 4A and 4B are schematic plan views of an embodiment ofthe display panel 10. In detail, FIGS. 3AA, AB, 4A and 4B are plan viewsillustrating the shapes of the side display area SDA and the cornerdisplay area CDA of the display panel 10 which are not yet bent. Inother words, FIGS. 3AA, AB, 4A and 4B are plan views of the side displayarea SDA and the corner display area CDA of the display panel 10 whichare in unbent states. FIG. 3B is a magnified plan view of a firstportion AR1 of FIG. 3AA and FIG. 3C is a magnified plan view of a secondportion AR2 of FIG. 3AA. FIG. 3DA illustrates cross-sectional views of adata line DL of FIG. 3B and a pixel circuit PC of FIG. 3C taken alonglines and II-IP, respectively. FIG. 4A corresponds to a partialmodification of FIG. 3AA, and thus will be described by focusing ondifferences from FIG. 3AA. Reference numerals in FIGS. 3AA, AB, 4A and4B that are the same as the reference numerals in FIG. 1 denote the sameelements, and thus repeated descriptions thereof are omitted.

The display panel 10 may include a display element. In an embodiment,the display panel 10 may be an organic light-emitting display panelusing an organic light-emitting diode including an organic emissionlayer, a micro light-emitting diode display panel using a microlight-emitting diode, a quantum dot light-emitting display panel using aquantum dot light-emitting diode including a quantum dot emission layer,or an inorganic light-emitting display panel using an inorganiclight-emitting element including an inorganic semiconductor, forexample. A case where the display panel 10 is an organic light-emittingdisplay panel using an organic light-emitting diode as a display elementwill now be focused on and described in detail.

Referring to FIG. 3AA, the display panel 10 may include a display areaDA and a peripheral area PA. The display area DA displays an image by aplurality of pixels PX, and the peripheral area PA may surround at leasta portion of the display area DA. The display area DA may include afront display area FDA, a side display area SDA, a corner display areaCDA, and a middle display area MDA.

The display panel 10 may include a substrate 100, and a multi-layerarranged on the substrate 100. The display area DA and the peripheralarea PA may be defined in the substrate 100 and/or the multi-layer. Inother words, the substrate 100 and/or the multi-layer may include thefront display area FDA, the side display area SDA, the corner displayarea CDA, the middle display area MDA, and the peripheral area PA.

In an embodiment, the substrate 100 may include polymer resin such asglass, polyethersulphone, polyacrylate, polyetherimide, polyethylenenaphthalate, polyethylene terephthalate, polyphenylene sulfide,polyimide, polycarbonate, cellulose triacetate, or cellulose acetatepropionate. The substrate 100 including polymer resin may have flexible,rollable, and bendable characteristics. The substrate 100 may have amulti-layered structure including a base layer including theaforementioned polymer resin and a barrier layer (not shown).

Each of the pixels PX may include subpixels, and each of the subpixelsmay emit light of a predetermined color by an organic light-emittingdiode as a display element. In an embodiment, each organiclight-emitting diode may emit, for example, red light, green light, orblue light, for example. Each organic light-emitting diode may beconnected to a pixel circuit including a thin-film transistor and astorage capacitor.

The peripheral area PA does not provide an image, and thus may be anon-display area. The peripheral area PA may include a bending area BA.The peripheral area PA extending from a lower end portion of the displayarea DA in the first direction (for example, the y direction) mayinclude the bending area BA. The peripheral area PA may be bent at thebending area BA. When a front side of the display panel 10 is viewedwhile the bending area BA is being bent, a portion of the peripheralarea PA may not be visually recognized by a user.

In the peripheral area PA, a driving circuit DC for providing anelectrical signal to each pixel PX through a signal line, a voltage wirefor providing a voltage, for example, may be arranged. The drivingcircuit DC may include a gate driving circuit GDC and a data drivingcircuit DDC.

The gate driving circuit GDC may transmit a gate signal to each pixel PXvia a gate line GL. The gate line GL may extend in the second direction(for example, the x direction) and may be connected to pixels PXdisposed on the same row. The gate line GL may include a scan line SLand a light-emission control line EL, and the gate signal may include ascan signal and a light-emission control signal. The gate drivingcircuit GDC may include a scan driving circuit, and may transmit a scansignal to each pixel PX through a scan line SL. The gate driving circuitGDC may include a light-emission control driving circuit, and mayprovide a light-emission control signal to each pixel PX through alight-emission control line EL.

The gate driving circuit GDC may be on one side of the peripheral areaPA. In an embodiment, as shown in FIG. 3AA, the gate driving circuit GDCmay be arranged in a portion of the peripheral area PA that correspondsto a lower end portion of the display panel 10, for example, forexample. In another embodiment, the gate driving circuit GDC may bearranged in a portion of the peripheral area PA that corresponds to theleft side or right side of the display panel 10.

The gate line GL may be connected to the gate driving circuit GDC via agate connection line GCL. The gate connection line GCL may extend in thefirst direction (for example, the y direction) intersecting the seconddirection (for example, the x direction), one side of the gateconnection line GCL may be connected to the gate driving circuit GDC,and the other side thereof may be connected to the gate line GL. Thegate driving circuit GDC may transmit the gate signal to each pixel PXvia the gate connection line GCL and the gate line GL.

FIG. 3C illustrates some of a plurality of pixel circuits PC arranged ina row direction (x direction) and a column direction (y direction). Eachof the scan line SL and the light-emission control line EL may extend inthe second direction (for example, the x direction), and a first dataline DL1 that is the data line DL may extend in the first direction (forexample, the y direction). The gate connection line GCL that connectseach of the scan line SL and the light-emission control line EL to thegate driving circuit GDC may extend in the first direction (for example,the y direction). The gate connection line GCL may extend in the samedirection as the extension direction of the first data line DL1.

In an embodiment, as shown in FIG. 3C, one gate connection line GCL mayoverlap one pixel circuit PC. Pixel circuits PC arranged on the samecolumn may be overlapped by the same gate connection line GCL. Inanother embodiment, two or more gate connection lines GCL may overlapone pixel circuit PC. In other words, the pixel circuits PC arranged onthe same column may be overlapped by two or more gate connection linesGCL.

In an embodiment, the gate connection line GCL may be in a differentlayer from the layer in which the scan line SL and the light-emissioncontrol line EL are. Referring to FIG. 3DA, insulating layers such as afirst gate insulating layer 112 and a second gate insulating layer 113may be between the gate connection line GCL and the scan line SL and thelight-emission control line EL. In this case, the gate connection lineGCL may be connected to the scan line SL and the light-emission controlline EL through a contact hole CNT defined in the first gate insulatinglayer 112 and the second gate insulating layer 113.

In FIG. 3DA, the gate connection line GCL is arranged on the second gateinsulating layer 113. However, in another embodiment, the gateconnection line GCL may be on the first gate insulating layer 112. Thefirst gate insulating layer 112 may be between the gate connection lineGCL and the scan line SL and the light-emission control line EL.

The contact hole CNT connecting the scan line SL and/or thelight-emission control line EL to the gate connection line GCL may bedefined in at least one pixel circuit PC from among the pixel circuitsPC arranged on the same row. In an embodiment, two or more pixelcircuits PC from among a plurality of pixel circuits PC arranged on thesame row may be connected to the gate connection line GCL through thecontact hole CNT, for example.

In an embodiment, the gate connection line GCL may be in the same layeras the layer in which the first data line DL1 is. Referring to FIG. 3DA,the gate connection line GCL and the first data line DL1 may be on aninterlayer insulating layer 114.

Referring back to FIG. 3AA, the data driving circuit DDC may be on thesame side as the gate driving circuit GDC. In an embodiment, the datadriving circuit DDC may be on one side of the peripheral area PA,together with the gate driving circuit GDC. In an embodiment, as shownin FIG. 3AA, the data driving circuit DDC together with the gate drivingcircuit GDC may be arranged in the portion of the peripheral area PAcorresponding to the lower end portion of the display panel 10, forexample. In another embodiment, the data driving circuit DDC togetherwith the gate driving circuit GDC may be arranged in the portion of theperipheral area PA corresponding to the left side or right side of thedisplay panel 10.

As a comparative example, a data driving circuit and a gate drivingcircuit may be arranged on respective one sides of different peripheralareas, respectively. The data driving circuit may be in the lower endportion of a display panel, and the gate driving circuit may be on theleft and/or right sides of the display panel. In this case, according tothe layout of the gate driving circuit, a dead space on the left and/orright sides of the display panel may increase, for example.

In contrast, both the data driving circuit DDC and the gate drivingcircuit GDC in an embodiment may be on one side of the peripheral areaPA. As shown in FIG. 3AA, when both the data driving circuit DDC and thegate driving circuit GDC are arranged in the lower end portion of thedisplay panel 10, dead spaces on the left and right sides of the displaypanel 10 may decrease. The display area DA on which an image isdisplayed may increase by as much as the area by which the dead spaceson the left and right sides of the display panel 10 decrease.

The data driving circuit DDC may transmit a data signal to each pixel PXvia the data line DL. The data line DL may extend in the first direction(for example, the y direction) and may be connected to pixels PXdisposed on the same column.

The data line DL may include a first data line DL1 arranged incorrespondence with the front display area FDA, and a second data lineDL2 arranged adjacent to the edge of the display area DA. As shown inFIG. 3AA, the second data line DL2 may be arranged to correspond to theside display area SDA. The second data line DL2 may also be arranged ina portion of the front display area FDA that is adjacent to the sidedisplay area SDA.

The first data line DL1 may be connected to the data driving circuit DDCthrough a first data connection line DCL1. One side of the first dataconnection line DCL1 may be connected to the data driving circuit DDC,and the other side thereof may be connected to the first data line DL1.The first data connection line DCL1 may be arranged to correspond to theperipheral area PA.

The second data line DL2 may be connected to the data driving circuitDDC through a second data connection line DCL2. One side of the seconddata connection line DCL2 may be connected to the data driving circuitDDC, and the other side thereof may be connected to the second data lineDL2.

In an embodiment, as shown in FIG. 3AA, a portion of the second dataconnection line DCL2 may overlap the peripheral area PA, and the otherportion of the second data connection line DCL2 may overlap the frontdisplay area FDA. The second data connection line DCL2 may be bent atleast once in the front display area FDA. A portion of the second dataconnection line DCL2 may extend from the front display area FDA in thesecond direction (for example, the x direction).

FIG. 3B illustrates magnified portions of the second data line DL2 andthe second data connection line DCL2. A portion of the second dataconnection line DCL2 may extend in the second direction (for example,the x direction). The second data connection line DCL2 may extend in thefirst direction (for example, the y direction).

In an embodiment, the second data line DL2 and the second dataconnection line DCL2 may be in different layers. Referring to FIG. 3DA,an insulating layer such as a first planarization layer 115 may bebetween the second data line DL2 and the second data connection lineDCL2. In this case, the second data line DL2 and the second dataconnection line DCL2 may be connected to each other through a contacthole CNT′ defined in the first planarization layer 115.

In an embodiment, as shown in FIG. 4B, a portion of the second dataconnection line DCL2 may overlap the peripheral area PA, and the otherportion of the second data connection line DCL2 may overlap the middledisplay area MDA. In this case, the second data connection line DCL2 maynot be bent in the front display area FDA, and may extend along themiddle display area MDA. The second data connection line DCL2 mayinclude a curve that follows the middle display area MDA.

The peripheral area PA may include a pad unit (not shown) that is anarea where an electronic device, a printed circuit board, or the likemay be electrically connected. The pad unit may be exposed without beingcovered with an insulating layer, and may be electrically connected to aflexible printed circuit board (“FPCB”) 30. The FPCB 30 may electricallyconnect a controller to the pad unit, and may provide a signal or powerreceived from the controller. In an embodiment, the gate driving circuitGDC and/or the data driving circuit DDC may be arranged on the FPCB 30.

Referring to FIG. 3AB which is an enlarged view of a portion AA of FIG.3AA, the corner display area CDA may include second pixels PX2 eachincluding a corner display element, and may be bent. In other words, asdescribed above with reference to FIG. 1, the corner display area CDAmay extend from the corner of the front display area FDA and may be bentwith an arbitrary radius of curvature, while being arranged tocorrespond to the corner portion CP.

When the corner display area CDA is bent, a compressive strain may begenerated more greatly than a tensile strain in the corner display areaCDA. In this case, a shrinkable substrate and a shrinkable multi-layeredstructure need to be applied to the corner display area CDA.Accordingly, the shape of a stack of multiple layers or a substrate 100arranged in the corner display area CDA may be different from that of astack of multiple layers or a substrate 100 arranged in the frontdisplay area FDA. In an embodiment, the corner display area CDA mayinclude a plurality of strip portions each extending in a direction awayfrom the front display area FDA, and a space may be between adjacentstrip portions. This will be described later in detail with reference toFIGS. 5A and 5B.

In an embodiment, the second pixels PX2 may be electrically connected topixel circuits arranged in the front display area FDA and/or the sidedisplay area SDA. In another embodiment, the second pixels PX2 may beelectrically connected to pixel circuits arranged in the corner displayarea CDA. In this case, the pixel circuits arranged in the cornerdisplay area CDA may share various wires connected to the pixel circuitsarranged in the front display area FDA and/or the side display area SDA.The pixel circuits arranged in the corner display area CDA may provide ascan signal, a data signal, and the like through the wires. This will bedescribed later in detail with reference to FIGS. 12A through 12E.

Third pixels PX3 each including a middle display element may be arrangedin the middle display area MDA between the front display area FDA andthe corner display area CDA. In an embodiment, as shown in FIG. 3AB, avoltage wire VWL for providing a voltage may be arranged in the middledisplay area MDA. In this case, the third pixels PX3 arranged in themiddle display area MDA may overlap the voltage wire VWL. By reference,the voltage wire VWL is indicated by a two-dot-dashed line in FIG. 3AB.

Referring to FIG. 4B which is an enlarged view of a portion CC of FIG.4A, the second data connection line DCL2 may be arranged in the middledisplay area MDA between the front display area FDA and the cornerdisplay area CDA. As described above, the second data connection lineDCL2 may connect the second data line DL2 to the data driving circuitDDC.

When the second data connection line DCL2 is arranged in the middledisplay area MDA, the third pixels PX3 arranged in the middle displayarea MDA may overlap the second data connection line DCL2. The pixelcircuits electrically connected to the third pixels PX3 may be arrangedin the front display area FDA and/or the side display area SDA.

Multiple layers stacked on a display panel will now be described indetail with reference to FIG. 3DA.

Referring to FIG. 3DA, the display panel may include the substrate 100,a buffer layer 111, a pixel circuit layer PCL, a display element layerDEL, and a thin-film encapsulation layer TFE.

The buffer layer 111 may include an inorganic insulating material, suchas silicon nitride, silicon oxynitride, or silicon oxide, and may be asingle layer or multiple layers including the inorganic insulatingmaterial.

The pixel circuit layer PCL may be on the buffer layer 111. The pixelcircuit layer PCL may include a thin-film transistor TFT included in apixel circuit PC, an inorganic insulating layer IIL, a firstplanarization layer 115, and a second planarization layer 116, where theinorganic insulating layer IIL, the first planarization layer 115, andthe second planarization layer 116 arranged below and/or over thecomponents of the thin-film transistor TFT. The inorganic insulatinglayer IIL may include the first gate insulating layer 112, the secondgate insulating layer 113, and the interlayer insulating layer 114.

The thin-film transistor TFT may include a semiconductor layer A, andthe semiconductor layer A may include polysilicon. In an alternativeembodiment, the semiconductor layer A may include, for example,amorphous silicon, an oxide semiconductor, or an organic semiconductor.The semiconductor layer A may include a channel region, and a sourceregion and a drain region respectively arranged on both sides of thechannel region. A gate electrode G may overlap the channel region.

The gate electrode G may include a low resistance metal material. In anembodiment, the gate electrode G may include a conductive materialincluding at least one of molybdenum (Mo), aluminum (Al), copper (Cu),and titanium (Ti), and may be a multi-layer or single layer includingthe aforementioned materials, for example. In an embodiment, the scanline SL and the light-emission control line EL may be arranged in thesame layer as the layer in which the gate electrode G is arranged. Thescan line SL and the light-emission control line EL may be on the firstgate insulating layer 112.

In an embodiment, the first gate insulating layer 112 between thesemiconductor layer A and the gate electrode G may include an inorganicinsulating material such as silicon oxide (SiO₂), silicon nitride(SiN_(X)), silicon oxynitride (SiON), aluminum oxide (Al₂O₃), titaniumoxide (TiO₂), tantalum oxide (Ta₂O₅), hafnium oxide (HfO₂), or zincoxide (ZnO₂).

In an embodiment, the second gate insulating layer 113 may cover thegate electrode G. Similar to the first gate insulating layer 112, thesecond gate insulating layer 113 may include an inorganic insulatingmaterial such as silicon oxide (SiO₂), silicon nitride (SiN_(X)),silicon oxynitride (SiON), aluminum oxide (Al₂O₃), titanium oxide(TiO₂), tantalum oxide (Ta₂O₅), hafnium oxide (HfO₂), or zinc oxide(ZnO₂).

An upper electrode CE2 of a storage capacitor Cst may be on the secondgate insulating layer 113. The upper electrode CE2 may overlap the gateelectrode G. The gate electrode G and the upper electrode CE2overlapping each other with the second gate insulating layer 113therebetween may constitute the storage capacitor Cst of the pixelcircuit PC. In other words, the gate electrode G may function as a lowerelectrode CE1 of the storage capacitor Cst. In this way, the storagecapacitor Cst and the thin-film transistor TFT may overlap each other.In an embodiment, the storage capacitor Cst and the thin-film transistorTFT may not overlap each other.

In an embodiment, the upper electrode CE2 may include at least one ofaluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium(Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium(Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), andcopper (Cu), and may each be a single layer or multi-layer including theaforementioned materials, for example.

The interlayer insulating layer 114 may cover the upper electrode CE2.In an embodiment, the interlayer insulating layer 114 may includesilicon oxide (SiO₂), silicon nitride (SiN_(x)), silicon oxynitride(SiON), aluminum oxide (Al₂O₃), titanium oxide (TiO₂), tantalum oxide(Ta₂O₅), hafnium oxide (HfO₂), zinc oxide (ZnO₂), or the like, forexample. The interlayer insulating layer 114 may be a single layer ormulti-layer including the aforementioned inorganic insulating material.

The data line DL, the gate connection line GCL, a drain electrode D, anda source electrode S may be disposed on the interlayer insulating layer114. The data line DL, the gate connection line GCL, the drain electrodeD, and the source electrode S may include a highly conductive material.In an embodiment, the data line DL, the gate connection line GCL, thedrain electrode D, and the source electrode S may include a conductivematerial including at least one of Mo, Al, Cu, and T1, and may be amulti-layer or single layer including the aforementioned materials, forexample. In an embodiment, the data line DL, the gate connection lineGCL, the drain electrode D, and the source electrode S may have amulti-layered structure of Ti/Al/Ti.

The first planarization layer 115 may cover the data line DL, the gateconnection line GCL, the drain electrode D, and the source electrode S.The first planarization layer 115 may include an organic insulatingmaterial. In an embodiment, the first planarization layer 115 mayinclude an organic insulating material, such as a commercial polymer(such as polymethyl methacrylate (“PMMA”) or polystyrene (“PS”)), apolymer derivative having a phenol-based group, an acryl-based polymer,an imide-based polymer, an acryl ether-based polymer, an amide-basedpolymer, a fluorine-based polymer, a p-xylene-based polymer, a vinylalcohol-based polymer, or a combination thereof.

A connecting electrode CML and the second data connection line DCL2 maybe on the first planarization layer 115. The connecting electrode CMLmay be connected to the drain electrode D or the source electrode Sthrough a contact hole of the first planarization layer 115. The seconddata connection line DCL2 may be connected to the second data line DL2through the contact hole CNT' of the first planarization layer 115.

The connecting electrode CML and the second data connection line DCL2may include a highly conductive material. In an embodiment, theconnecting electrode CML may include a conductive material including atleast one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium(Ti), and may be a multi-layer or single layer including theaforementioned materials, for example. In an embodiment, the connectingelectrode CML and the second data connection line DCL2 may have amulti-layer structure of Ti/Al/Ti.

A second planarization layer 116 may cover the connecting electrode CMLand the second data connection line DCL2. The second planarization layer116 may include an organic insulating layer. In an embodiment, thesecond planarization layer 116 may include an organic insulatingmaterial, such as a commercial polymer (such as PMMA or PS), a polymerderivative having a phenol-based group, an acryl-based polymer, animide-based polymer, an acryl ether-based polymer, an amide-basedpolymer, a fluorine-based polymer, a p-xylene-based polymer, a vinylalcohol-based polymer, or a combination thereof

The display element layer DEL may be on the pixel circuit layer PCL. Thedisplay element layer DEL may include a first display element DEl. Thefirst display element DE1 may be an organic light-emitting diode OLED(refer to FIG. 6). A pixel electrode 211 of the first display elementDE1 may be electrically connected to the connecting electrode CMLthrough a contact hole of the second planarization layer 116.

In an embodiment, the pixel electrode 211 may include conductive oxidesuch as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide(ZnO), indium oxide (In₂O₃), indium gallium oxide (“IGO”), or aluminumzinc oxide (“AZO”). In another embodiment, the pixel electrode 211 mayinclude a reflection layer including, for example, silver (Ag),magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au),nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compoundof these materials. In another embodiment, the pixel electrode 211 mayfurther include a film including ITO, IZO, ZnO, or In₂O₃ above/below theaforementioned reflection layer.

An opening 118OP through which a center portion of the pixel electrode211 is exposed may be defined in a pixel defining layer 118 arranged onthe pixel electrode 211. The pixel defining layer 118 may include anorganic insulating material and/or an inorganic insulating material. Theopening 118OP may define a light-emission area (hereinafter, alsoreferred to as a light-emission area EA1) of light emitted by the firstdisplay element DEl. In an embodiment, a width of the opening 118OP maycorrespond to a width of the light-emission area EA1 of the firstdisplay element DE1, for example.

A spacer 119 may be on the pixel defining layer 118. The spacer 119 maybe included to prevent damage to the substrate 100, in a method ofmanufacturing a display apparatus. The display panel may be manufacturedusing a mask sheet. In this case, when the mask sheet enters the opening118OP of the pixel defining layer 118 or closely adheres to the pixeldefining layer 118 and a deposition material is deposited on thesubstrate 100, the spacer 119 may prevent a portion of the substrate 100from being damaged or destructed by the mask sheet.

The spacer 119 may include an organic insulating material such aspolyimide. In an alternative embodiment, the spacer 119 may include aninorganic insulating material such as silicon nitride or silicon oxide,or may include an inorganic insulating material and an organicinsulating material.

In an embodiment, the spacer 119 may include a material different fromthat included in the pixel defining layer 118. In another embodiment,the spacer 119 may include the same material as that included in thepixel defining layer 118. In this case, the pixel defining layer 118 andthe spacer 119 may be provided together in a mask process using ahalftone mask or the like.

An intermediate layer 212 may be on the pixel defining layer 118. Theintermediate layer 212 may include an emission layer 212 b arranged inthe opening 118OP of the pixel defining layer 118. The emission layer212 b may include a low molecular or high molecular organic materialthat emits light of a predetermined color.

A first functional layer 212 a and a second functional layer 212 c maybe arranged below and above the emission layer 212 b, respectively. Thefirst functional layer 212 a may include a hole transport layer (“HTL”),or may include an HTL and a hole injection layer (“HIL”). The secondfunctional layer 212 c is a component arranged above the emission layer212 b, and is optional. The second functional layer 212 c may include anelectron transport layer (“ETL”) and/or an electron injection layer(“EIL”). The first functional layer 212 a and/or the second functionallayer 212 c may be a common layer covering the entire surface of thesubstrate 100, similar to an opposite electrode 213 to be describedlater.

The opposite electrode 213 may include a conductive material having alow work function. In an embodiment, the opposite electrode 213 mayinclude a (semi)transparent layer including, for example, silver (Ag),magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au),nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li),calcium (Ca) or an alloy of these materials, for example. In analternative embodiment, the opposite electrode 213 may further include alayer, such as ITO, IZO, ZnO, or In₂O₃, on the (semi)transparent layerincluding any of the above-described materials.

In an embodiment, a capping layer (not shown) may be further arranged onthe opposite electrode 213. The capping layer may include lithiumfluoride (LiF), an inorganic material, or/and an organic material.

The thin-film encapsulation layer TFE may be on the opposite electrode213. In an embodiment, the thin-film encapsulation layer TFE includes atleast one inorganic encapsulation layer and at least one organicencapsulation layer. FIG. 3DA illustrates the thin-film encapsulationlayer TFE including a first inorganic encapsulation layer 310, anorganic encapsulation layer 320, and a second inorganic encapsulationlayer 330 sequentially stacked on each other.

The first inorganic encapsulation layer 310 and the second inorganicencapsulation layer 330 may include at least one inorganic material fromamong aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide,zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. Theorganic encapsulation layer 320 may include a polymer-based material.Examples of the polymer-based material may include an acrylic resin, anepoxy-based resin, polyimide, and polyethylene. In an embodiment, theorganic encapsulation layer 320 may include acrylate.

Although not shown in the drawings, a touch electrode layer may bearranged on the thin-film encapsulation layer TFE, and an opticalfunctional layer may be arranged on the touch electrode layer. The touchscreen layer may obtain coordinate information based on an externalinput, for example, a touch event. The optical functional layer mayreduce reflectance of light (external light) externally incident towardthe display apparatus, and/or may improve color purity of light emittedby the display apparatus. In an embodiment, the optical functional layermay include a phase retarder and/or a polarizer. The phase retarder maybe of a film type or liquid coating type, and may include a 212 phaseretarder and/or a λ/4 phase retarder. The polarizer may also be of afilm type or liquid coating type. The film type may include astretchable synthetic resin film, and the liquid coating type mayinclude liquid crystals arranged in a predetermined arrangement. Thephase retarder and the polarizer may further include protective films,respectively.

In another embodiment, the optical functional layer may include a blackmatrix and color filters. The color filters may be arranged by takinginto account the colors of light beams emitted by the pixels of thedisplay apparatus. Each of the color filters may include a pigment ordyes of a red, green, or blue color. In an alternative embodiment, eachof the color filters may further include quantum dots in addition to theabove-described pigment or dyes. In an alternative embodiment, some ofthe color filters may not include the above-described pigment or dyes,and may include scattered particles such as titanium oxide.

In another embodiment, the optical functional layer may include adestructive interference structure. The destructive interferencestructure may include a first reflection layer and a second reflectionlayer arranged in different layers. First reflected light and secondreflected light respectively reflected by the first reflection layer andthe second reflection layer may be destructively interfered with eachother, and thus the reflectance of external light may be reduced.

An adhesion member may be between the touch electrode layer and theoptical functional layer. The adhesion member may employ a generaladhesion member known to the art without limitation. The adhesion membermay be a pressure sensitive adhesive (“PSA”).

FIGS. 5AA to 5BB are schematic plan views of an embodiment of amagnified portion of the display panel 10. In detail, FIGS. 5AA and 5ABmay be understood as illustrating an unfolded display panel 10 before anexternal force is applied thereto, and FIGS. 5BA and 5BB may beunderstood as illustrating a display panel 10 deformed after an externalforce is applied thereto.

Referring to FIGS. 5AA and 5AB, the display panel 10 may include aplurality of strip portions STP arranged to correspond to the cornerdisplay area CDA, and a plurality of spaces V may be defined between theplurality of strip portions STP and penetrate through the display panel10. Because the display panel 10 includes the substrate 100, it may beconsidered that the substrate 100 has the plurality of strip portionsSTP and that the plurality of spaces V is defined in the substrate 100.

Respective one ends of the plurality of strip portions STP may be spacedapart from each other by a gap gp. Empty spaces may be defined betweenthe plurality of strip portions STP due to the gap gp, and maycorrespond to the plurality of spaces V, respectively. The gap gpbetween the plurality of strip portions STP may vary. In an embodiment,as shown in FIG. 5AA, the gap gp between the plurality of strip portionsSTP may widen in a direction from the middle display area MDA to thecorner display area CDA, for example. In another embodiment, the gap gpbetween the plurality of strip portions STP may not vary but may beconstant. In other words, the plurality of strip portions STP may bearranged radially or in parallel.

Respective other ends of the plurality of strip portions STP may not bespaced apart from each other but may be connected to each other. Asshown in FIG. 5AA, the plurality of strip portions STP may be connectedto each other near the middle display area MDA. The plurality of stripportions STP may each extend from the middle display area MDA to thecorner display area CDA, and may form the plurality of spaces V definedbetween the plurality of strip portions STP. Respective extensionlengths of the plurality of strip portions STP may be different from oneanother. The respective extension lengths of the plurality of stripportions STP may be different from one another according to distances bywhich the plurality of strip portions STP are spaced apart from themiddle area of the corner display area CDA. In an embodiment, stripportions STP disposed in the middle from among the plurality of stripportions STP may have greater lengths extending toward the cornerdisplay area CDA than those of the other strip portions STP, and therespective extension lengths of the plurality of strip portions STP maydecrease as distances by which the plurality of strip portions STP isspaced apart from the middle area of the corner display area CDAincrease, for example.

Each of the spaces V may penetrate through a front surface and a bottomsurface of the display panel 10. Each of the spaces V may reduce theweight of the display panel 10 and may improve flexibility of thedisplay panel 10. When an external force (e.g., a warping, bending, orpulling force) is applied to the display panel 10, the shapes of thespaces V change, and thus stress generation during deformation of thedisplay panel 10 is easily reduced. Thus, abnormal deformation of thedisplay panel 10 may be prevented, and durability of the display panel10 may improve. Accordingly, when an electronic device including thedisplay panel 10 is used, user's convenience may improve, and thedisplay panel 10 may be easily applied to wearable devices.

Referring to FIG. SBB, when an external force is applied to the displaypanel 10, the area or shape of each space V′ may be changed, and thelocation of each strip portion STP may also be changed. In anembodiment, when a bending force is exerted on the edges of the displaypanel 10 and a corner between the edges, the area of the space V′ maydecrease with a decrease in a gap gp′ between the plurality of stripportions STP, and neighboring strip portions STP may contact each other,for example.

When an external force is applied to the display panel 10 as describedabove, the gap gp' between the plurality of strip portions STP and thearea of the space V′ may change, but there may be no changes in theshapes of the plurality of strip portions STP. In other words, a pixelcircuit, a display element, and the like may be arranged on each of theplurality of strip portions STP, and the shapes of the plurality ofstrip portions STP do not change even when an external force is appliedto the display panel 10, and thus the pixel circuit, the displayelement, and the like arranged on each of the plurality of stripportions STP may be protected. Thus, pixels may also be arranged in thecorner display area CDA of the display panel 10 having a curvature.Accordingly, the display area DA may expand from the front display areaFDA to the corner display area CDA.

A plurality of pixels PX may be arranged on each strip portion STP. Theplurality of pixels PX arranged on the strip portion STP may be spacedapart from each other in one direction. The plurality of pixels PX maybe arranged in various configurations such as a stripe configuration, ans-stripe configuration, and a PenTile configuration.

FIG. 6 is a schematic equivalent circuit diagram of an embodiment of apixel circuit PC applicable to a display panel.

Referring to FIG. 6, the pixel circuit PC may be connected to a scanline SL, a data line DL, and a display element DE. The display elementDE may be an organic light-emitting diode OLED.

The pixel circuit PC may include a driving thin-film transistor T1, ascan thin-film transistor T2, and a storage capacitor Cst. The scanthin-film transistor T2 is connected to the scan line SL and the dataline DL, and transmits, to the driving thin-film transistor T1, a datavoltage Dm received via the data line DL according to a scan signal Snreceived via the scan line SL where n and m are natural numbers.

The storage capacitor Cst is connected to the scan thin-film transistorT2 and a driving voltage line PL, and stores a voltage corresponding toa difference between a voltage received from the scan thin-filmtransistor T2 and a driving voltage ELVDD supplied to the drivingvoltage line PL.

The driving thin-film transistor T1 is connected to the driving voltageline PL and the storage capacitor Cst, and may control a driving currentflowing from the driving voltage line PL to the organic light-emittingdiode OLED, in accordance with a voltage value stored in the storagecapacitor Cst. The organic light-emitting diode OLED may emit lighthaving a predetermined brightness due to the driving current.

Although a case where the pixel circuit PC includes two thin-filmtransistors and one storage capacitor is illustrated in FIG. 6,embodiments are not limited thereto. In an embodiment, the pixel circuitPC may include three or more thin-film transistors and/or two or morestorage capacitors, for example. In another embodiment, the pixelcircuit PC may include seven thin-film transistors and one storagecapacitor. This will now be described with reference to FIG. 7.

FIG. 7 is a schematic equivalent circuit diagram of an embodiment of apixel circuit PC applicable to a display panel.

Referring to FIG. 7, the pixel circuit PC may be connected to a scanline SL, a data line DL, and a display element DE. The display elementDE may be an organic light-emitting diode OLED.

In an embodiment, as shown in FIG. 7, the pixel circuit PC includesfirst through seventh thin-film transistors T1 through T7 and a storagecapacitor Cst, for example. The first through seventh thin-filmtransistors T1 through T7 and the storage capacitor Cst are connected tofirst through third scan lines SL, SL-1, and SL+1 for respectivelytransmitting first through third scan signals Sn, Sn−1, and Sn+1, a dataline DL for transmitting a data voltage Dm, a light-emission controlline EL for transmitting a light-emission control signal En, a drivingvoltage line PL for transmitting a driving voltage ELVDD, aninitializing voltage line VL for transmitting an initializing voltageVint, and a common electrode to which a common voltage ELVSS is applied.

The first thin-film transistor T1 is a driving transistor in which themagnitude of a drain current is determined according to a gate-sourcevoltage, and the second through seventh thin-film transistors T2 throughT7 may be switching transistors that are turned on/off according to thegate-source voltage, substantially, a gate voltage.

The first thin-film transistor T1 may be also referred to as a drivingthin-film transistor, the second thin-film transistor T2 may be alsoreferred to as a scan thin-film transistor, the third thin-filmtransistor T3 may be also referred to as a compensating thin-filmtransistor, the fourth thin-film transistor T4 may be also referred toas a gate initializing thin-film transistor, the fifth thin-filmtransistor T5 may be also referred to as a first light-emission controlthin-film transistor, the sixth thin-film transistor T6 may be alsoreferred to as a second light-emission control thin-film transistor, andthe seventh thin-film transistor T7 may be also referred to as an anodeinitializing thin-film transistor.

The storage capacitor Cst is connected between the driving voltage linePL and a driving gate G1 of the driving thin-film transistor T1. Thestorage capacitor Cst may have an upper electrode CE2 connected to thedriving voltage line PL, and a lower electrode CE1 connected to thedriving gate G1 of the driving thin-film transistor T1.

The driving thin-film transistor T1 may control the magnitude of adriving current I_(OLED) flowing from the driving voltage line PL to theorganic light-emitting diode OLED according to the gate-source voltage.The driving thin-film transistor T1 may include the driving gate G1connected to the lower electrode CE1 of the storage capacitor Cst, adriving source S1 connected to the driving voltage line PL through thefirst light-emission control thin-film transistor T5, and a drivingdrain D1 connected to the organic light-emitting diode OLED through thesecond light-emission control thin-film transistor T6.

The driving thin-film transistor T1 may output the driving currentI_(OLED) to the organic light-emitting diode OLED according to thegate-source voltage. The magnitude of the driving current I_(OLED) isdetermined based on a difference between the gate-source voltage and athreshold voltage of the driving thin-film transistor Ti. The organiclight-emitting diode OLED may receive the driving current I_(OLED) fromthe driving thin-film transistor T1, and emit light with a brightnessbased on the magnitude of the driving current I_(OLED).

The scan thin-film transistor T2 transmits the data voltage Dm to thedriving source S1 of the driving thin-film transistor T1 in response tothe first scan signal Sn. The scan thin-film transistor T2 may include ascan gate G2 connected to the first scan line SL, a scan source S2connected to the data line DL, and a scan drain D2 connected to thedriving source S1 of the driving thin-film transistor T1.

The compensating thin-film transistor T3 is serially connected betweenthe driving drain D1 and the driving gate G1 of the driving thin-filmtransistor T1, and connects the driving drain D1 and the driving gate G1of the driving thin-film transistor T1 to each other in response to thefirst scan signal Sn. The compensating thin-film transistor T3 mayinclude a compensating gate G3 connected to the first scan line SL, acompensating source S3 connected to the driving drain D1 of the drivingthin-film transistor T1, and a compensating drain D3 connected to thedriving gate G1 of the driving thin-film transistor T1. Although thecompensating thin-film transistor T3 has two thin-film transistorsserially connected to each other in FIG. 7, the compensating thin-filmtransistor T3 may include one thin-film transistor.

The gate initializing thin-film transistor T4 applies an initializingvoltage Vint to the driving gate G1 of the driving thin-film transistorT1 in response to the second scan signal Sn−1.The gate initializingthin-film transistor T4 may include a first initializing gate G4connected to the second scan line SL−1, a first initializing source S4connected to the driving gate G1 of the driving thin-film transistor T1,and a first initializing drain D4 connected to the initializing voltageline VL. Although the gate initializing thin-film transistor T4 includestwo thin-film transistors serially connected to each other in FIG. 7,the gate initializing thin-film transistor T4 may include one thin-filmtransistor.

The anode initializing thin-film transistor T7 applies the initializingvoltage Vint to an anode of the organic light-emitting diode OLED inresponse to the third scan signal Sn+1. The anode initializing thin-filmtransistor T7 may include a second initializing gate G7 connected to thethird scan line SL+1, a second initializing source S7 connected to theanode of the organic light-emitting diode OLED, and a secondinitializing drain D7 connected to the initializing voltage line VL.

The first light-emission control thin-film transistor T5 may connect thedriving voltage line PL to the driving source S1 of the drivingthin-film transistor T1 in response to the light-emission control signalEn. The first light-emission control thin-film transistor T5 may includea first light-emission control gate G5 connected to the light-emissioncontrol line EL, a first light-emission control source S5 connected tothe driving voltage line PL, and a first light-emission control drain D5connected to the driving source S1 of the driving thin-film transistorT1.

The second light-emission control thin-film transistor T6 may connectthe driving drain D1 of the driving thin-film transistor T1 to the anodeof the organic light-emitting diode OLED in response to thelight-emission control signal En. The second light-emission controlthin-film transistor T6 may include a second light-emission control gateG6 connected to the light-emission control line EL, a secondlight-emission control source S6 connected to the driving drain D1 ofthe driving thin-film transistor T1, and a second light-emission controldrain D6 connected to the anode of the organic light-emitting diodeOLED.

The second scan signal Sn-1 may be substantially synchronized with afirst scan signal Sn on a previous row. The third scan signal Sn+1 maybe substantially synchronized with the first scan signal Sn. In anotherembodiment, the third scan signal Sn+1 may be substantially synchronizedwith a first scan signal Sn on a next row.

In the illustrated embodiment, the first through seventh thin-filmtransistors T1 through T7 may include semiconductor layers includingsilicon. In an embodiment, the first through seventh thin-filmtransistors T1 through T7 may include semiconductor layers including lowtemperature polysilicon (“LTPS”). Because a polysilicon material has ahigh electron mobility (100 square centimeters per volt per second(cm²/Vs) or greater), energy consumption power is low and reliability ishigh, for example. In another embodiment, the semiconductor layers ofthe first through seventh thin-film transistors T1 through T7 mayinclude oxide including at least one of indium (In), gallium (Ga), tin(Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd),germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium(Cs), cerium (Ce), and zinc (Zn). In an embodiment, the semiconductorlayers of the first through seventh thin-film transistors T1 through T7may be an InSnZnO (“ITZO”) semiconductor layer, an InGaZnO (“IGZO”)semiconductor layer, or the like, for example. In another embodiment,some of the semiconductor layers of the first through seventh thin-filmtransistors T1 through T7 may include LTPS, and others thereof mayinclude an oxide semiconductor (e.g., IGZO or the like).

Operations of one pixel circuit PC and an organic light-emitting diodeOLED, as a display element DE, of the display panel 10 in an embodimentwill now be described in detail. As shown in FIG. 7, the first throughseventh thin-film transistors T1 through T7 are assumed to be p-typemetal-oxide-semiconductor field-effect transistors (“MOSFETs”).

First, in response to a light-emission control signal En of a highlevel, the first light-emission control thin-film transistor T5 and thesecond light-emission control thin-film transistor T6 are turned off,and the driving thin-film transistor T1 stops outputting the drivingcurrent I_(OLED) and the organic light-emitting diode OLED stopsemitting light.

Thereafter, during a gate initialization period when a second scansignal Sn-1 of a low level is received, the gate initializing thin-filmtransistor T4 is turned on, and the initializing voltage Vint is appliedto the driving gate G1 of the driving thin-film transistor T1, namely,to the lower electrode CE1 of the storage capacitor Cst. The storagecapacitor Cst stores a difference (ELVDD-Vint) between the drivingvoltage ELVDD and the initializing voltage Vint.

Then, during a data write period when a first scan signal Sn of a lowlevel is received, the scan thin-film transistor T2 and the compensatingthin-film transistor T3 are turned on, and the data voltage Dm isreceived by the driving source S1 of the driving thin-film transistorT1. The driving thin-film transistor T1 is diode-connected by thecompensating thin-film transistor T3 and is biased in a forwarddirection. The gate voltage of the driving thin-film transistor T1increases from the initializing voltage Vint. When the gate voltage ofthe driving thin-film transistor T1 becomes equal to a data compensatingvoltage (Dm−|Vth|) obtained by reducing a threshold voltage Vth of thedriving thin-film transistor T1 from the data voltage Dm, the drivingthin-film transistor T1 is turned off and at the same time the gatevoltage of the driving thin-film transistor T1 stops increasing.Accordingly, the storage capacitor Cst stores a difference(ELVDD−Dm+|Vth|) between the driving voltage ELVDD and the datacompensating voltage (Dm−|Vth|).

During an anode initialization period when a third scan signal Sn+1 of alow level is received, the anode initializing thin-film transistor T7 isturned on, and the initializing voltage Vint is applied to the anode ofthe organic light-emitting diode OLED. By allowing the organiclight-emitting diode OLED to completely emit no light by applying theinitializing voltage Vint to the anode of the organic light-emittingdiode OLED, a pixel PX receives a data voltage Dm corresponding to ablack grayscale in a next frame, but minute light emission of theorganic light-emitting diode OLED may be prevented.

The first scan signal Sn and the third scan signal Sn+1 may besubstantially synchronized with each other. In this case, the data writeperiod and the anode initialization period may be the same periods.

Thereafter, in response to a light-emission control signal En of a lowlevel, the first light-emission control thin-film transistor T5 and thesecond light-emission control thin-film transistor T6 may be turned on,the driving thin-film transistor T1 may output a driving currentI_(OLED) corresponding to a voltage (ELVDD - Dm) obtained by subtractingthe threshold voltage |Vth| of the driving thin-film transistor T1 froma voltage stored in the storage capacitor Cst, namely, the source-gatevoltage (ELVDD−Dm+|Vth|) of the driving thin-film transistor T1, and theorganic light-emitting diode OLED may emit light with a brightnesscorresponding to the magnitude of the driving current I_(OLED).

FIGS. 8A and 8B are schematic plan views of an embodiment of a magnifiedportion of the display panel 10. In detail, FIGS. 8A and 8B aremagnified plan views schematically illustrating the corner portion CP ofthe display panel 10. FIG. 8B corresponds to a partial modification ofFIG. 8A, and thus will be described by focusing on differences from FIG.8A.

Referring to FIG. 8A, a plurality of first pixels PX1 may be arranged inthe front display area FDA and/or the side display area SDA. Each of theplurality of first pixels PX1 may include a first red subpixel Pr1, afirst green subpixel Pg1, and a first blue subpixel Pb1. In anembodiment, the first pixel PX1 includes subpixels arranged in a PenTileconfiguration. In this case, one first red subpixel Pr1, two first greensubpixels Pg1, and one first blue subpixel Pb1 may constitute one firstpixel PX1.

A plurality of second pixel pixels PX2 may be arranged in the cornerdisplay area CDA, and a plurality of third pixels PX3 may be arranged inthe middle display area MDA. Each of the plurality of second pixelpixels PX2 may include a second red subpixel Pr2, a second greensubpixel Pg2, and a second blue subpixel Pb2, and each of the pluralityof third pixels PX3 may include a third red subpixel Pr3, a third greensubpixel Pg3, and a third blue subpixel Pb3. Although a plurality ofthird pixels PX3 is arranged in one column along the middle display areaMDA in FIG. 8A, the plurality of third pixels PX3 may be also arrangednear the side of the corner display area CDA and/or the front displayarea FDA and thus may be arranged in a plurality of columns.

In an embodiment, each second pixel PX2 and each third pixel PX3 mayhave the same subpixel layouts. The subpixel layout of the second pixelPX2 may be the same as that of the third pixel PX3.

In an embodiment, as shown in FIG. 8A, the second pixels PX2 and thethird pixels PX3 may have stripe subpixel layouts, for example. Inanother embodiment, as shown in FIG. 8B, the second pixels PX2 and thethird pixels PX3 may have s-stripe subpixel layouts. In anotherembodiment, the second pixels PX2 and the third pixels PX3 may havePenTile subpixel layouts.

In another embodiment, each second pixel PX2 and each third pixel PX3may have different subpixel layouts. The subpixel layout of the secondpixel PX2 may be different from that of the third pixel PX3. In anembodiment, each second pixel PX2 may have a stripe type layout, andeach third pixel PX3 may have an s-stripe type or PenTile type layout,for example.

Each of the second pixel PX2 and the third pixel PX3 may includesubpixels. When each second pixel PX2 has a stripe type or s-stripe typelayout, one second red subpixel Pr2, one second green subpixel Pg2, andone second blue subpixel Pb2 may constitute one second pixel PX2. Wheneach third pixel PX3 has a stripe type or s-stripe type layout, onethird red subpixel Pr3, one third green subpixel Pg3, and one third bluesubpixel Pb3 may constitute one third pixel PX3.

In an embodiment, a planar area of each second pixel PX2 may be the sameas that of each third pixel PX3. The second pixel PX2 may include acorner display element (hereinafter, a second display element) DE2(refer to FIGS. 11AA and 11C), and the planar area of the second pixelPX2 may be defined as the area of a light-emission area EA2 (refer toFIG. 11C) of the second display element DE2. Although the second pixelPX2 has been focused on and described above, this description is equallyapplicable to the third pixel PX3. The third pixel PX3 may include amiddle display element (hereinafter, a third display element) DE3 (referto FIGS. 11AA and 11C), and the planar area of the third pixel PX3 maybe defined as the area of a light-emission area EA3 (refer to FIG. 11C)of the third display element DE3. In another embodiment, a planar areaof each second pixel PX2 may be different from that of each third pixelPX3. In other words, the area of the light-emission region EA2 of thesecond display element DE2 may be different from that of thelight-emission region EA3 of the third display element DE3.

When the planar area of the second pixel PX2 is equal to the planar areaof the third pixel PX3 and the second pixel PX2 and the third pixel PX3have the same type layouts, an image quality difference between thecorner display area CDA and the middle display area MDA may be preventedor minimized.

The planar areas of the second pixel PX2 and the third pixel PX3 may begreater than the planar area of the first pixel PX1. The first pixel PX1may include the first display element DE1 (refer to FIGS. 3DA or 11A),and the planar area of the first pixel PX1 may be defined as the area ofthe light-emission area EA1 (refer to FIG. 3DA) of the first displayelement DE1 . In other words, the areas of the light-emission areas EA2and EA3 of the second display element DE2 and the third display elementDE3 may be greater than the area of the light-emission region EA1 of thefirst display element DE1 . The number (i.e., resolution) of pixelsarranged per unit area of the corner display area CDA and the middledisplay area MDA may be less than that of the front display area FDAand/or the side display area SDA. Instead, because a space where thesecond pixels PX2 and the third pixels PX3 may be arranged may be moresecured, the second pixels PX2 and the third pixels PX3 may have largeplanar areas, and thus life spans of the second pixels PX2 and the thirdpixels PX3 may increase.

As described above with reference to FIG. 3AB, the voltage wire VWL maybe arranged in the middle display area MDA disposed between the cornerdisplay area CDA and the front display area FDA. The third pixels PX3arranged in the middle display area MDA may overlap the voltage wireVWL. In this case, because pixels may also be arranged in the area wherethe voltage wire VWL is arranged, the area may be used as the displayarea DA. The voltage wire VWL may be the initializing voltage line VL(refer to FIG. 7) and/or a common voltage line. The initializing voltageVint (refer to FIG. 7), the common voltage ELVSS (refer to FIG. 7), andthe like may be applied to the voltage wire VWL.

In an embodiment, as will be described later with reference to FIGS.11AA and 11AB, the second pixels PX2 arranged in the corner display areaCDA may be electrically connected to the pixel circuits arranged in thefront display area FDA and/or the side display area SDA. The thirdpixels PX3 arranged in the middle display area MDA may be electricallyconnected to the pixel circuits arranged on the front display area FDAand/or the side display area SDA.

In another embodiment, as will be described later with reference to FIG.12A, the second pixels PX2 arranged in the corner display area CDA maybe electrically connected to the pixel circuits arranged in the cornerdisplay area CDA.

FIG. 9 is a schematic plan view of an embodiment of a magnified portionof the display panel 10. In detail, FIG. 9 is a magnified plan viewschematically illustrating the corner portion CP of the display panel10. FIG. 9 corresponds to a partial modification of FIG. 8A, and thuswill be described by focusing on differences from FIG. 8A.

Referring to FIG. 9, a first voltage wire VWL1 and a second voltage wireVWL2 may be arranged in the peripheral area PA of the display panel 10.The first voltage wire VWL1 and the second voltage wire VWL2 may bespaced apart from each other with the middle display area MDAtherebetween. The first voltage wire VWL1 and the second voltage wireVWL2 may be connected to each other through a voltage connection lineVCL.

The voltage connection line VCL may be arranged in the corner displayarea CDA, and may be arranged along the edge of the corner display areaCDA. In an embodiment, the voltage connection line VCL may be arrangedalong the edges of the plurality of strip portions STP, for example.Each of the plurality of strip portions STP may extend from the middledisplay area MDA to the corner display area CDA. Because the voltageconnection line VCL is arranged along the edges of the plurality ofstrip portions STP, a portion of the voltage connection line VCL mayextend from the middle display area MDA to the corner display area CDA.Because the voltage connection line VCL is arranged in the cornerdisplay area CDA, a portion of the voltage connection line VCL mayinclude a curve.

In FIG. 9, the first voltage wire VWL1 and the second voltage wire VWL2are connected to the voltage connection line VCL arranged on the edge ofthe corner display area CDA, and thus, in contrast with FIG. 8A, novoltage wires VWL may be arranged in the middle display area MDA.Accordingly, pixel circuits may also be arranged in the middle displayarea MDA. The third pixels PX3 arranged in the middle display area MDAmay be electrically connected to the pixel circuits arranged in themiddle display area MDA.

The pixel circuits electrically connected to the third pixels PX3arranged in the middle display area MDA may be arranged in the frontdisplay area FDA and/or the side display area SDA.

FIG. 10 is a schematic plan view of another embodiment of a magnifiedportion of the display panel 10. In detail, FIG. 10 is a magnified planview schematically illustrating the corner portion CP of the displaypanel 10. FIG. 10 corresponds to a partial modification of FIG. 8A, andthus will be described by focusing on differences from FIG. 8A.

Referring to FIG. 10, as described above with reference to FIG. 4B, asecond data connection line DCL2 may be arranged in the middle displayarea MDA. The second data connection line DCL2 may connect the datadriving circuit DDC to the second data line DL2.

When the second data connection line DCL2 is arranged in the middledisplay area MDA, the third pixels PX3 arranged in the middle displayarea MDA may overlap the second data connection line DCL2. In anembodiment, the third pixels PX3 may be arranged on the second dataconnection line DCL2, for example.

When the third pixels PX3 are overlapped by the second data connectionline DCL2, the pixel circuits electrically connected to the third pixelsPX3 may be arranged in the front display area FDA and/or the sidedisplay area SDA.

FIG. 11AA is a plan view of a layout of pixel circuits PC and displayelements DE of the display panel 10 in an embodiment, and FIG. 11B is across-sectional view of a bridge line BL of FIG. 11AB taken along lineIII-IIP.

FIG. 11AA illustrates an embodiment of a layout of pixel circuits anddisplay elements of each of the front display area FDA and/or the sidedisplay area SDA, the middle display area MDA, and the corner displayarea CDA. In particular, FIG. 11AA focuses on and illustrates a layoutof pixel circuits and display elements of each of the middle displayarea MDA and the corner display area CDA. Although a boundary betweenthe front display area FDA and/or the side display area SDA and themiddle display area MDA is indicated by a dotted straight line in FIG.11AA, the boundary may be a curve. This may be equally applied to aboundary between the middle display area MDA and the corner display areaCDA.

Referring to FIG. 11AA, first pixels PX1 may be arranged in the frontdisplay area FDA and/or the side display area SDA. Each first pixel PX1may include a first display element DE1. The first display element DE1may be electrically connected to a first pixel circuit PC1 through acontact line CTL. In this case, the first pixel circuit PC1 may bearranged in the front display area FDA and/or the side display area SDAwhere the first display element DE1 is arranged. The first displayelement DE1 may overlap the first pixel circuit PC1.

Third pixels PX3 may be arranged in the middle display area MDA. Eachthird pixel PX3 may include a third display element DE3. The thirddisplay element DE3 may be electrically connected to a middle pixelcircuit (hereinafter, a third pixel circuit) PC3 through a first bridgeline BL1. In this case, the third pixel circuit PC3 may be arranged inthe front display area FDA and/or the side display area SDA. Accordingto a layout of the third display element DE3 and the third pixel circuitPC3, the first bridge line BL1 may vary. At least a portion of the firstbridge line BL1 may extend from the front display area FDA toward themiddle display area MDA.

As described above with reference to FIGS. 8A and 10, the voltage wireVWL and/or the data connection line DCL may be arranged in the middledisplay area MDA. Because the voltage wire VWL and/or the dataconnection line DCL are arranged in the middle display area MDA, a spacewhere the third pixel circuits PC3 are to be arranged may beinsufficient. Instead, the third pixel circuits PC3 may be arranged notin the middle display area MDA but in portions of the front display areaFDA and/or the side display area SDA that are adjacent to the middledisplay area MDA. The third pixel circuit PC3 and the third displayelement DE3 may be spaced apart from each other. In this way, the thirdpixel circuits PC3 for the third pixels PX3 are arranged in portions ofthe front display area FDA and/or the side display area SDA that areadjacent to the middle display area MDA, and the third pixel circuitsPC3 are electrically connected to the third display elements DE3arranged in the middle display area MDA through the first bridge linesBL1, and thus the display area may expand to the middle display area MDAwhere the voltage wire VWL and/or the data connection line DCL arearranged.

In another embodiment, as described above with reference to FIG. 9, whenno voltage wires VWL, no data connection lines DCL, and the like arearranged in the middle display area MDA, the third pixel circuits PC3may be arranged in the middle display area MDA. In this case, similar tothe first display element DE1, the third display element DE3 may beconnected to the third pixel circuit PC3 through the contact line CTL.The third display element DE3 may overlap the third pixel circuit PC3.

Second pixels PX2 may be arranged in the corner display area CDA. Eachsecond pixel PX2 may include a second display element DE2. The seconddisplay element DE2 may be electrically connected to a corner pixelcircuit (hereinafter, a second pixel circuit) PC2 through a secondbridge line BL2. In this case, the second pixel circuit PC2 may bearranged in the front display area FDA and/or the side display area SDA.According to layouts of the second display element DE2 and the secondpixel circuit PC2, the second bridge line BL2 may vary. At least aportion of the second bridge line BL2 may extend from the front displayarea FDA toward the corner display area CDA.

In an embodiment, a plurality of pixels arranged in the middle displayarea MDA and the corner display area CDA may be sequentially connectedto a plurality of pixel circuits arranged in the front display area FDAand/or the side display area SDA. In an embodiment, as shown in FIG.11AA, the third pixels PX3 arranged in the middle display area MDA maybe closer to the front display area FDA and/or the side display area SDAthan the second pixels PX2 arranged in the corner display area CDA are,for example. In this case, the third pixels PX3 may be connected to thethird pixel circuits PC3 closest to the first pixels PX1. This may beequally applied to the second pixels PX2 arranged in the corner displayarea CDA. In an embodiment, a second pixel PX2 closest to the middledisplay area MDA may be connected to a second pixel circuit PC2 closestto a third pixel circuit PC3, for example. A second pixel PX2 arrangedat an end of a strip portion STP may be connected to a second pixelcircuit PC2 farthest from the third pixel circuit PC3. In anotherembodiment, the second pixel PX2 closest to the middle display area MDAmay be connected to the second pixel circuit PC2 farthest from the thirdpixel circuit PC3. The second pixel PX2 arranged at an end of the stripportion STP may be connected to the second pixel circuit PC2 closest tothe third pixel circuit PC3.

Referring to FIG. 11AB which is an enlarged view of a portion FF of FIG.11AA, the second bridge line BL2 for connecting the second pixel PX2 tothe second pixel circuit PC2 may be overlapped by the first bridge lineBL1 for connecting the third pixel PX3 to the third pixel circuit PC3.

In an embodiment, the second bridge line BL2 may include a first portionBL2 a and a second portion BL2 b. The first portion BL2 a may beoverlapped by the first bridge line BL1. The first portion BL2 a and thefirst bridge line BL1 may be in different layers. Referring to FIG. 11B,an insulating layer such as the first planarization layer 115 may bebetween the first portion BL2 a and the first bridge line BL1. The firstportion BL2 a and the second portion BL2 b may be connected to eachother through a first contact hole CNT1 and a second contact hole CNT2defined in the first planarization layer 115. In this case, even whenthe first bridge line BL1 and the second bridge line BL2 overlap eachother, they may not be electrically connected to each other. Althoughthe second bridge line BL2 includes the first portion BL2 a and thesecond portion BL2 b in FIG. 11AB, the first bridge line BL1 may includea first portion and a second portion arranged in different layers. Acase where the first bridge line BL1 and the second bridge line BL2overlap each other has been illustrated as an example, but thisdescription may be equally applied to a case where the first bridgelines BL1 overlap each other or the second bridge lines BL2 overlap eachother.

FIG. 11C is a cross-sectional view of the front display area FDA, themiddle display area MDA, and the corner display area CDA of FIG. 11AAtaken along lines IV-IV′ and V-V′, and FIG. 11D is a cross-sectionalview of the front display area FDA and the middle display area MDA ofFIG. 11AA taken along lines VI-VI′ and VII-VII′. Reference numerals inFIGS. 11C and 11D that are the same as the reference numerals in FIG.3DA denote the same elements, and thus repeated descriptions thereof areomitted.

Referring to FIGS. 11C and 11D, a display panel may include the cornerdisplay area CDA, the middle display area MDA and the front display areaFDA. For convenience of explanation, the front display area FDA has beenfocused on described. However, this description may be equally appliedto the side display area SDA. The corner display area CDA may include asecond display element DE2, and the middle display area MDA may includea third display element DE3. In an embodiment, the second displayelement DE2 and the third display element DE3 may be organiclight-emitting diodes OLED, for example.

In the illustrated embodiment, the second display element DE2 arrangedin the corner display area CDA may be electrically connected to thesecond pixel circuit PC2 arranged in the front display area FDA. Thethird display element DE3 arranged in the middle display area MDA may beelectrically connected to the third pixel circuit PC3 arranged in thefront display area FDA.

Multiple layers stacked in the corner display area CDA, the middledisplay area MDA, and the front display area FDA will now be describedin detail.

In the corner display area CDA, the middle display area MDA, and thefront display area FDA, the substrate 100, the buffer layer 111, thepixel circuit layer PCL, the display element layer DEL, and thethin-film encapsulation layer TFE may be stacked. The pixel circuitlayer PCL may include an inorganic insulating layer IIL, a voltage wireVWL, a bridge line BL, a first planarization layer 115, a secondplanarization layer 116, and the like.

A buffer layer 111 may be arranged on the substrate 100, and theinorganic insulating layer IIL may be arranged on the buffer layer 111.In an embodiment, the inorganic insulating layer IIL may include a firstgate insulating layer 112, a second gate insulating layer 113, and aninterlayer insulating layer 114.

The voltage wire VWL may be on the inorganic insulating layer IIL. Thevoltage wire VWL may be arranged to correspond to the middle displayarea MDA. In an embodiment, the initializing voltage Vint, the commonvoltage ELVSS, and the like of FIG. 7 may be applied to the voltage wireVWL, for example.

The first planarization layer 115 may be on the inorganic insulatinglayer IIL, and the first planarization layer 115 may cover the voltagewire VWL. The bridge line BL may be on the first planarization layer115.

First, referring to FIG. 11C, the second bridge line BL2 may extend fromthe front display area FDA to the corner display area CDA. The secondbridge line BL2 may overlap the front display area FDA, the middledisplay area MDA, and the corner display area CDA. On end of the secondbridge line BL2 may be connected to the second pixel circuit PC2arranged in the front display area FDA, and the other end of the secondbridge line BL2 may be connected to the second display element DE2arranged in the corner display area CDA. The second display element DE2may be electrically connected to the second pixel circuit PC2 throughthe second bridge line BL2.

Referring to FIG. 11D, the first bridge line BL1 may extend from thefront display area FDA to the middle display area MDA. The first bridgeline BL1 may overlap the front display area FDA and the middle displayarea MDA. On end of the first bridge line BL1 may be connected to thethird pixel circuit PC3 arranged in the front display area FDA, and theother end of the first bridge line BL1 may be connected to the thirddisplay element DE3 arranged in the middle display area MDA. The thirddisplay element DE3 may be electrically connected to the third pixelcircuit PC3 through the first bridge line BL1.

Although the first bridge line BL1 and the second bridge line BL2 areboth on the first planarization layer 115 in FIGS. 11C and 11D, thefirst bridge line BL1 and the second bridge line BL2 may be on the firstgate insulating layer 112 or the second gate insulating layer 113.

The first bridge line BL1 and the second bridge line BL2 may be indifferent layers. In an embodiment, the first bridge line BL1 may be onthe first gate insulating layer 112, and the second bridge line BL2 maybe on the first planarization layer 115, for example.

A first inorganic pattern layer PVX1 may be on the bridge line BL. In anembodiment, a plurality of first inorganic pattern layers PVX1 may be onthe bridge line BL, and may be spaced apart from each other on thebridge line BL.

The second planarization layer 116 may cover the bridge line BL. In anembodiment, the second planarization layer 116 may be a lower layer thatdefines a groove Gv. A hole H may be defined in the second planarizationlayer 116. In this case, the hole H may correspond to the firstinorganic pattern layer PVX1. The second planarization layer 116 maycover the edge of the first inorganic pattern layer PVX1. Accordingly,the groove Gv may be defined by a center portion of the first inorganicpattern layer PVX1 and the hole H of the second planarization layer 116.

A second inorganic pattern layer PVX2 may be on the second planarizationlayer 116. Second inorganic pattern layers PVX2 may be on both sides ofthe groove Gv, and may have a pair of protruding tips PT protruding in acenter direction of the groove Gv. In this case, a first functionallayer 212 a, a second functional layer 212 c, and an opposite electrode213 (refer to FIG. 3DA) arranged on the second inorganic pattern layerPVX2 may be disconnected by the groove Gv and the pair of protrudingtips PT. The first functional layer pattern 212Pa, the second functionallayer pattern 212Pc, and the opposite electrode 213 may be within thegroove Gv.

A dam unit DP protruding in a thickness direction of the substrate 100may be above the second inorganic pattern layer PVX2. In an embodiment,the dam unit DP may include a first dam unit DP1 and a second dam unitDP2. In an embodiment, the dam unit DP and the groove Gv may alternatewith each other. In an embodiment, a first groove Gv1, a first dam unitDP1, a second groove Gv2, a second dam unit DP2, and a third groove Gv3may be sequentially arranged in a direction from the corner display areaCDA to the middle display area MDA, for example.

The dam unit DP may include first layers 118 a and 118 b, and secondlayers 119 a and 119 b on the first layers 118 a and 118 b. In thiscase, the first layers 118 a and 118 b may include the same material asa material included in the pixel defining layer 118. The first layers118 a and 118 b may be simultaneously provided when the pixel defininglayer 118 is provided. The second layers 119 a and 119 b include thesame material as a material included in the spacer 119 of FIG. 3DA. Thesecond layers 119 a and 119 b may be simultaneously provided when thespacer 119 is provided.

The thin-film encapsulation layer TFE may cover the second displayelement DE2 and the third display element DE3. The thin-filmencapsulation layer TFE may include at least one inorganic encapsulationlayer and at least one organic encapsulation layer. FIGS. 11C and 11Dillustrate that the thin-film encapsulation layer TFE includes a firstinorganic encapsulation layer 310, an organic encapsulation layer 320,and a second inorganic encapsulation layer 330.

The thin-film encapsulation layer TFE may extend from the second displayelement DE2 to the first dam unit DP1. The thin-film encapsulation layerTFE may extend from the third display element DE3 to the second dam unitDP2.

The first inorganic encapsulation layer 310 may entirely andconsecutively cover the corner display area CDA, the middle display areaMDA, and the front display area FDA. In detail, the first inorganicencapsulation layer 310 may be entirely and consecutively arranged inthe first groove Gv1, the first dam unit DP1, the second groove Gv2, thesecond dam unit DP2, and the third groove Gv3. The first inorganicencapsulation layer 310 may cover the first functional layer pattern212Pa, the second functional layer pattern 212Pc, and the oppositeelectrode 213 arranged within the groove Gv.

The organic encapsulation layer 320 may be broken up by the dam unit DP.In an embodiment, the organic encapsulation layer 320 may extend fromthe second display element DE2 to the first dam unit DP1 and may fillthe first groove Gv1, for example. The organic encapsulation layer 320may extend from the third display element DE3 to the second dam unit DP2and may fill the third groove Gv3. In other words, the organicencapsulation layer 320 may be controlled by the first dam unit DP1 andthe second dam unit DP2. In this case, the second groove Gv2 may not befilled with the organic encapsulation layer 320.

Similar to the first inorganic encapsulation layer 310, the secondinorganic encapsulation layer 330 may entirely and consecutively coverthe corner display area CDA, the middle display area MDA, and the frontdisplay area FDA. In an embodiment, the second inorganic encapsulationlayer 330 may contact the first inorganic encapsulation layer 310 on thefirst dam unit DP1 and the second dam unit DP2. The second inorganicencapsulation layer 330 may contact the first inorganic encapsulationlayer 310 in the second groove Gv2. Accordingly, the organicencapsulation layer 320 may be broken up by the dam unit DP. In anembodiment, at least one of the first layers 118 a and 118 b and thesecond layers 119 a and 119 b of the dam unit DP may be omitted, and theorganic encapsulation layer 320 may extend from the middle display areaMDA to the corner display area CDA. In other words, the organicencapsulation layer 320 may be integrally included in the middle displayarea MDA and the corner display area CDA.

FIG. 12A is a schematic plan view of another embodiment of a layout ofpixel circuits PC and display elements DE of the display panel 10. FIG.12A corresponds to a partial modification of FIG. 11AA, and thus will bedescribed by focusing on differences from FIG. 11AA.

FIG. 12A illustrates another embodiment of a layout of pixel circuitsand display elements of each of the front display area FDA and/or theside display area SDA, the middle display area MDA, and the cornerdisplay area CDA.

Referring to FIG. 12A, second pixels PX2 may be arranged in the cornerdisplay area CDA. Each second pixel PX2 may include a second displayelement DE2. The second display element DE2 may be electricallyconnected to a second pixel circuit PC2. In contrast with FIG. 11AA, thesecond pixel circuit PC2 may be arranged in the corner display area CDA,like the front display area FDA and/or the side display area SDA. Inother words, the second pixel circuit PC2 may be arranged in the cornerdisplay area CDA, and may be electrically connected to the seconddisplay element DE2. The second display element DE2 may overlap thesecond pixel circuit PC2.

The second pixel circuit PC2 arranged in the corner display area CDA mayshare various wires with a first pixel circuit PC1 arranged in the frontdisplay area FDA and/or the side display area SDA. This will bedescribed later in more detail with reference to FIGS. 12B through 12D.

Third pixels PX3 may be arranged in the middle display area MDA. Eachthird pixel PX3 may include a third display element DE3. The thirddisplay element DE3 may be electrically connected to a third pixelcircuit PC3. In this case, the third pixel circuit PC3 may be arrangedin the front display area FDA and/or the side display area SDA.

FIG. 12B is a schematic plan view of another embodiment of a magnifiedportion of a display panel 10. In detail, FIG. 12B is a magnified planview schematically illustrating a corner portion CP of the display panel10.

Referring to FIG. 12B, the display panel 10 may include a substrate 100,first wires WL1, second wires WL2, corner wires CWL, and pixel circuitsPC. Each corner wire CWL may include a first corner wire CWLa and asecond corner wire CWLb.

The substrate 100 may include a display area and a peripheral area PA.The display area may include the front display area FDA, a first sidedisplay area SDA1 connected to the front display area FDA in the firstdirection (for example, the y direction), a second side display areaSDA2 connect to the front display area FDA in the second direction (forexample, the x direction), and a corner display area CDA disposedbetween the first side display area SDA1 and the second side displayarea SDA2 and surrounding at least a portion of the front display areaFDA. The display area may include the middle display area MDA betweenthe front display area FDA and the corner display area CDA.

The first wires WL1 and/or the second wires WL2 may be arranged in oneof the front display area FDA, the first side display area SDA1, and thesecond side display area SDA2. In an embodiment, the first wires WL1extending in the first direction (for example, they direction) and thesecond wires WL2 extending in the second direction (for example, the xdirection) may be arranged in the front display area FDA, for example.

A voltage wire VWL may be arranged in the middle display area MDA. Thevoltage wire VWL may be arranged in an extension direction of the middledisplay area MDA. As described above with reference to FIG. 4B, a dataconnection line DCL in addition to the voltage wire VWL may be arrangedin the middle display area MDA.

The corner display area CDA may include a plurality of strip portionsSTP each extending in a direction away from the front display area FDA.The plurality of strip portions STP may each extend from the middledisplay area MDA, and a space V may be defined between adjacent stripportions STP.

Each of the plurality of strip portions STP may include a center areaCA, and a first outer area OA1 and a second outer area OA2 arranged onboth sides of the center area CA. In this case, the center area CA, thefirst outer area OA1, and the second outer area OA2 may each extend inthe same direction as the direction in which each of the plurality ofstrip portions STP extends. Pixel circuits PC may be arranged in thecenter area CA.

Each first wire WL1 may extend in the first direction (for example, they direction) in the front display area FDA. The first wire WL1 may alsoextend in the first direction (for example, they direction) in at leastone of the first side display area SDA1 and the second side display areaSDA2.

The first wire WL1 may transmit a data signal to at least one of thefirst side display area SDA1, the second side display area SDA2, and thefront display area FDA. The first wire WL1 may be connected to the firstcorner wire CWLa. In detail, the first wire WL1 may be connected to thefirst corner wire CWLa through the connection line CL.

The first wire WL1 may correspond to the data line DL of FIGS. 3AA and4A. The first wire WL1 may be connected to the data driving circuit DDCand may transmit a data signal to a pixel circuit disposed in at leastone of the first side display area SDA1, the second side display areaSDA2, and the front display area FDA. The first wire WL1 may beconnected to the data driving circuit DDC through the first dataconnection line DCL1 disposed in the peripheral area PA, as shown inFIG. 3AA, or may be connected to the data driving circuit DDC throughthe second data connection line DCL2 partially overlapping the frontdisplay area FDA. In another embodiment, as shown in FIGS. 4A and 4B,the first wire WL1 may be connected to the data driving circuit DDCthrough the second data connection line DCL2 disposed in the middledisplay area MDA.

In an embodiment, the first wire WL1 and the connection line CL may bein different layers. In an embodiment, an insulating layer may bebetween the first wire WL1 and the connection line CL, for example. Inthis case, the first wire WL1 and the connection line CL may beconnected to each other through a contact hole of the insulating layer.

The second wire WL2 may extend in the second direction (for example, thex direction) in the front display area FDA. The second wire WL2 may alsoextend in the second direction (for example, the x direction) in atleast one of the first side display area SDA1 and the second sidedisplay area SDA2.

The second wire WL2 may be connected to the gate driving circuit GDC. Indetail, the second wire WL2 may be connected to the gate driving circuitGDC via each gate connection line GCL. The gate connection line GCL mayextend in the first direction (for example, the y direction). One end ofthe gate connection line GCL may be connected to the gate drivingcircuit GDC, and the other end of the gate connection line GCL may beconnected to the second wire WL2.

The gate connection line GCL may be in the same layer as the layer inwhich the first wire WL is. In an embodiment, the gate connection lineGCL and the first wire WL1 may be on the same insulating layer, forexample. The gate connection line GCL and the second wire WL2 may be indifferent layers. In an embodiment, an insulating layer may be betweenthe gate connection line GCL and the second wire WL2. In this case, thegate connection line GCL and the second wire WL2 may be connected toeach other through a contact hole of the insulating layer, for example.

The second wire WL2 may extend in the second direction (for example, thex direction). Thus, the second wire WL2 may transmit a scan signal or alight-emission control signal to at least one of the first side displayarea SDA1, the second side display area SDA2, and the front display areaFDA. The second wire WL2 may be connected to the second corner wireCWLb.

The first corner wire CWLa may be arranged in the corner display areaCDA. The first corner wire CWLa may extend in a direction intersectingthe first direction (for example, the y direction) and the seconddirection (for example, the x direction) within the corner display areaCDA. The first corner wire CWLa may extend in a direction away from thefront display area FDA.

The first corner wire CWLa may be arranged on each of the plurality ofstrip portions STP. In this case, the first corner wire CWLa may extendin the same direction as the extension direction of each strip portionSTP. In an embodiment, the first corner wire CWLa may overlap the pixelcircuits PC. In another embodiment, the first corner wire CWLa may bespaced apart from the pixel circuits PC. In this case, the first cornerwire CWLa may be arranged in at least one of the first outer area OA1and the second outer area OA2.

The first corner wire CWLa may be connected to the first wire WL1. Indetail, the first corner wire CWLa may be connected to the first wireWL1 through the connection line CL. In an embodiment, the first cornerwire CWLa and the connection line CL may be in different layers. In anembodiment, an insulating layer may be between the first corner wireCWLa and the connection line CL, for example. In this case, the firstcorner wire CWLa and the connection line CL may be connected to eachother through a contact hole of the insulating layer. In an embodiment,the first corner wire CWLa and the first wire WL1 may be on the sameinsulating layer.

The connection line CL may extend from the middle display area MDA tothe corner display area CDA. The connection line CL may overlap thevoltage wire VWL arranged in the middle display area MDA. When the dataconnection line DCL is arranged in the middle display area MDA, theconnection line CL may overlap the data connection line DCL.

The first corner wire CWLa may be connected to the pixel circuits PCarranged on the plurality of strip portions STP. In an embodiment, whenthe first corner wire CWLa overlaps the pixel circuits PC, the firstcorner wire CWLa may be directly connected to the pixel circuits PC. Inanother embodiment, when the first corner wire CWLa is spaced apart fromthe pixel circuits PC, the first corner wire CWLa may be connected tothe pixel circuits PC through a bridge line (not shown).

The first corner wire CWLa may transmit a data signal to the pixelcircuits PC arranged on the plurality of strip portions STP. The firstcorner wire CWLa may transmit the data signal received through the firstwire WL1 and the connection line CL to the pixel circuits PC arranged onthe plurality of strip portions STP.

The second corner wire CWLb may be arranged in the corner display areaCDA. The second corner wire CWLb may extend in the directionintersecting the first direction (for example, the y direction) and thesecond direction (for example, the x direction) within the cornerdisplay area CDA. The second corner wire CWLb may extend in a directionaway from the front display area FDA. The second corner wire CWLb mayextend in the same direction as the extension direction of the firstcorner wire CWLa.

The second corner wire CWLb may be arranged on each of the plurality ofstrip portions STP. In this case, the second corner wire CWLb may extendin the same direction as the extension direction of each strip portionSTP. In an embodiment, the second corner wire CWLb may be spaced apartfrom the pixel circuits PC. In this case, the second corner wire CWLbmay be arranged in at least one of the first outer area OA1 and thesecond outer area OA2. In another embodiment, the second corner wireCWLb may overlap the pixel circuits PC.

The second corner wire CWLb may be connected to the second wire WL2. Thesecond corner wire CWLb may transmit a scan signal or a light-emissioncontrol signal.

The second corner wire CWLb may pass through the middle display area MDAand extend to the corner display area CDA. In an embodiment, the secondcorner wire CWLb may overlap the voltage wire VWL arranged in the middledisplay area MDA. When the data connection line DCL is arranged in themiddle display area MDA, a portion of the second corner wire CWLb mayoverlap the data connection line DCL.

The second corner wire CWLb may be connected to the pixel circuits PCarranged on the plurality of strip portions STP. In an embodiment, whenthe second corner wire CWLb is spaced apart from the pixel circuits PC,the second corner wire CWLb may be connected to the pixel circuits PCthrough the bridge line. In another embodiment, when the second cornerwire CWLb overlaps the pixel circuits PC, the second corner wire CWLbmay be directly connected to the pixel circuits PC.

Although not shown in FIG. 12B, in an embodiment, a common wire mayextend in the extension direction of each of the plurality of stripportions STP. The initializing voltage Vint, the common voltage ELVSS,and the like of FIG. 7 may be applied to the common wire. Theinitializing voltage Vint, the driving voltage ELVDD, and the like maybe supplied to the pixel circuits PC arranged in the corner display areaCDA through the common wire.

In the illustrated embodiment, the first wire WL1 for transmitting adata signal may extend in the first direction (for example, the ydirection). The second wire WL2 for transmitting a scan signal or alight-emission control signal may extend in the second direction (forexample, the x direction). In the illustrated embodiment, because thespace V is defined between adjacent strip portions STP, each of thefirst wire WL1 and the second wire WL2 may not extend in the firstdirection (for example, the y direction) and the second direction (forexample, the x direction). Accordingly, the first corner wire CWLa andthe second corner wire CWLb may each extend in the extension directionof each of the plurality of strip portion STP and may transmit the datasignal, the scan signal, and/or the light-emission control signal to thepixel circuits PC arranged on the plurality of strip portions STP. Thedata signal, the scan signal, the light-emission control signal, and thelike transmitted to the front display area FDA and/or the side displayarea SDA may also be transmitted to the corner display area CDA. Inother words, the wires arranged in the front display area FDA and/or theside display area SDA and the wires arranged in the corner display areaCDA may share the data signal, the scan signal, the light-emissioncontrol signal, and the like.

FIGS. 12C and 12D are schematic plan views of an embodiment of a cornerdisplay area. Reference numerals in FIGS. 12C and 12D that are the sameas the reference numerals in FIG. 12A denote the same elements, and thusrepeated descriptions thereof are omitted.

Referring to FIGS. 12C and 12D, a display panel may include a substrate,first wires, second wires, corner wires CWL, pixel circuits PC, andbridge lines BWL. Each corner wire CWL may include a first corner wireCWLa and a second corner wire CWLb.

The substrate may include a front display area, a corner display areaCDA surrounding the front display area, and a middle display area MDAbetween the front display area and the corner display area CDA. Thecorner display area CDA may include a plurality of strip portions STPeach extending from the middle display area MDA, and a space may bedefined between adjacent strip portions STP. FIGS. 12C and 12Dillustrate one strip portion STP from among the plurality of stripportions STP.

The strip portion STP may extend in a first extension direction EDR1.The first extension direction EDR1 may be the direction intersecting thefirst direction (for example, the y direction) and the second direction(for example, the x direction) of FIG. 12A.

The strip portion STP may include a center area CA, and a first outerarea OA1 and a second outer area OA2 arranged on both sides of thecenter area CA. The center area CA may extend in the first extensiondirection EDR1. The center area CA may be between the first outer areaOA1 and the second outer area OA2.

A pixel circuit PC and a first corner wire CWLa may be in the centerarea CA. A plurality of pixel circuits PC may be arranged on the stripportion STP. The plurality of pixel circuits PC may be arranged side byside in the first extension direction EDR1.

In an embodiment, each pixel circuit PC may include a first subpixelcircuit PCa, a second subpixel circuit PCb, and a third subpixel circuitPCc. In another embodiment, the pixel circuit PC may further include afourth subpixel circuit. Each of the first subpixel circuit PCa, thesecond subpixel circuit PCb, and the third subpixel circuit PCc maycorrespond to the second pixel circuit PC2 of FIG. 12A. A case whereeach pixel circuit PC includes the first subpixel circuit PCa, thesecond subpixel circuit PCb, and the third subpixel circuit PCc will nowbe focused on and described in detail.

The first subpixel circuit PCa, the second subpixel circuit PCb, and thethird subpixel circuit PCc may be arranged side by side. In anembodiment, the first subpixel circuit PCa, the second subpixel circuitPCb, and the third subpixel circuit PCc may be arranged side by side ina first vertical direction VDR1 perpendicular to the first extensiondirection EDR1, for example. In an embodiment, a plurality of firstsubpixel circuits PCa may be included in the strip portion STP, and theplurality of first subpixel circuits PCa may be arranged side by side inthe first extension direction EDR1. A plurality of second subpixelcircuits PCb may be included in the strip portion STP, and the pluralityof second subpixel circuits PCb may be arranged side by side in thefirst extension direction EDR1. A plurality of third subpixel circuitsPCc may be included in the strip portion STP, and the plurality of thirdsubpixel circuits PCc may be arranged side by side in the firstextension direction EDR1.

In the illustrated embodiment, the first corner wire CWLa may extend inthe first extension direction EDR1. The first corner wire CWLa mayoverlap the pixel circuits PC. The first corner wire CWLa may include afirst data line DL1′, a second data line DL2′, and a third data lineDL3′ each extending in the first extension direction EDR1 to be parallelwith each other.

The first data line DL1′ may be connected to first subpixel circuitsPCa. In an embodiment, the first data line DL1′ may be connected to eachof the plurality of first subpixel circuits PCa. Accordingly, theplurality of first subpixel circuits PCa may be all connected to thesingle first data line DL1′.

In an embodiment, the first data line DL1′ may include a first lowerdata line LDL1 and a first upper data line UDL1. The first lower dataline LDL1 may be arranged in the middle display area MDA, and the firstupper data line UDL1 may be arranged in the corner display area CDA. Thefirst lower data line LDL1 and the first upper data line UDL1 may be indifferent layers. In this case, the first upper data line UDL1 may beabove an insulating layer, and the first lower data line LDL1 may bebelow the insulating layer. The first upper data line UDL1 and the firstlower data line LDL1 may be connected to each other through a contacthole of the insulating layer. In another embodiment, the first lowerdata line LDL1 may be omitted. In this case, the first upper data lineUDL1 may extend to the middle display area MDA.

The second data line DL2′ may be connected to second subpixel circuitsPCb. In an embodiment, the second data line DL2′ may be connected toeach of the plurality of second subpixel circuits PCb. Accordingly, theplurality of second subpixel circuits PCb may be all connected to thesingle second data line DL2′.

In an embodiment, the second data line DL2′ may include a second lowerdata line LDL2 and a second upper data line UDL2. The second lower dataline LDL2 may be arranged in the middle display area MDA, and the secondupper data line UDL2 may be arranged in the corner display area CDA. Thesecond lower data line LDL2 and the second upper data line UDL2 may bein different layers. In this case, the second upper data line UDL2 maybe above an insulating layer, and the second lower data line LDL2 may bebelow the insulating layer. The second upper data line UDL2 and thesecond lower data line LDL2 may be connected to each other through acontact hole of the insulating layer. In another embodiment, the secondlower data line LDL2 may be omitted. In this case, the second upper dataline UDL2 may extend to the middle display area MDA.

The third data line DL3′ may be connected to third subpixel circuitsPCc. In an embodiment, the third data line DL3′ may be connected to eachof the plurality of third subpixel circuits PCc. Accordingly, theplurality of third subpixel circuits PCc may be all connected to thesingle third data line DL3′.

In an embodiment, the third data line DL3′ may include a third lowerdata line LDL3 and a third upper data line UDL3. The third lower dataline LDL3 may be arranged in the middle display area MDA, and the thirdupper data line UDL3 may be arranged in the corner display area CDA. Thethird lower data line LDL3 and the third upper data line UDL3 may be indifferent layers. In this case, the third upper data line UDL3 may beabove an insulating layer, and the third lower data line LDL3 may bebelow the insulating layer. The third upper data line UDL3 and the thirdlower data line LDL3 may be connected to each other through a contacthole of the insulating layer. In another embodiment, the third lowerdata line LDL3 may be omitted. In this case, the third upper data lineUDL3 may extend to the middle display area MDA.

Accordingly, even when N pixel circuits PC are arranged on the singlestrip portion STP, three first corner wires CWLa may be arranged.

In an embodiment, when the pixel circuit PC further includes the fourthsubpixel circuit, the first corner wire CWLa may further include afourth data line. In this case, even when N pixel circuits PC arearranged on the single strip portion STP, four first corner wires CWLamay be arranged.

The first outer area OA1 and the second outer area OA2 may each extendin the first extension direction EDR1. The second corner wire CWLb maybe arranged in the first outer area OA1) and the second outer area OA2.The second corner wire CWLb may extend in the first extension directionEDR1, which is the same direction as the extension direction of thefirst corner wire CWLa. The second corner wire CWLb may transmit a scansignal or a light-emission control signal to the pixel circuits PC.

The second corner wire CWLb may include a lower wire and an upper wirearranged in different layers. In an embodiment, the lower wire may becovered by an insulating layer, and the upper wire may be arranged onthe insulating layer, for example.

In an embodiment, referring to FIG. 12C, three pixel circuits PC may bearranged on the strip portion STP, for example. In this case, the secondcorner wire CWLb may include a first lower wire LWL1, a second lowerwire LWL2, a third lower wire LWL3, a fourth lower wire LWL4, a firstupper wire UWL1, and a second upper wire UWL2. In an embodiment, thefirst lower wire LWL1, the second lower wire LWL2, and the first upperwire UWL1 may be arranged in the first outer area OA1. The third lowerwire LWL3, the fourth lower wire LWL4, and the second upper wire UWL2may be arranged in the second outer area OA2.

The lower wire and the upper wire may alternate with each other in thefirst vertical direction VDR1. In an embodiment, the first lower wireLWL1, the first upper wire UWL1, and the second lower wire LWL2 may besequentially arranged in the first vertical direction VDR1, for example.The fourth lower wire LWL4, the second upper wire UWL2, and the thirdlower wire LWL3 may also be sequentially arranged in the first verticaldirection VDR1.

Because the second corner wire CWLb includes a lower wire and an upperwire arranged in different layers in at least one of the first outerarea OA1 and the second outer area OA2, the strip portion STP may have areduced width. The width of the strip portion STP is a width of thestrip portion STP in the first vertical direction VDR1.

In the illustrated embodiment, the second corner wire CWLb may beconnected to the bridge lines BWL. Thus, the second corner wire CWLb maybe connected to the pixel circuits PC through the bridge lines BWL. Inan embodiment, the second corner wire CWLb and the bridge lines BWL maybe in different layers. In an embodiment, an insulating layer may bearranged on the second corner wire CWLb, for example. The bridge linesBWL may be on the insulating layer. In this case, the second corner wireCWLb and the bridge lines BWL may be connected to each other through acontact hole of the insulating layer. In an embodiment, the bridge linesBWL may be in the same layer as the layer in which the first corner wireCWLa is. In an embodiment, the bridge lines BWL may be in the same layeras the layer in which the first upper data line UDL1 is, for example.

In the illustrated embodiment, the second corner wire CWLb may beconnected to two of the plurality of pixel circuits PC. In detail, aprevious scan line and a current scan line connected to adjacent pixelcircuits PC may be connected to the same second corner wire CWLb. In anembodiment, a first scan line SL1 and a second previous scan line SL2-1connected to pixel circuits PC may be connected to the first upper wireUWL1 through bridge lines BWL, for example. A second scan line SL2 and athird previous scan line SL3-1 connected to pixel circuits PC may beconnected to the third lower wire LWL3 through bridge lines BWL.

In an embodiment, light-emission control lines connected to adjacentpixel circuits PC may be connected to the same second corner wire CWLb.In an embodiment, a first light-emission control line EL1 and a secondlight-emission control line EL2 connected to adjacent pixel circuits PCmay be connected to the second lower wire LWL2 through bridge lines BWL,for example.

In another embodiment, light-emission control lines connected to pixelcircuits PC may each be connected to the second corner wire CWLb. A casewhere light-emission control lines connected to adjacent pixel circuitsPC are connected to the same second corner wire CWLb will now be focusedon and described in detail.

A first previous scan line SL1-1 connected to a pixel circuit PC may beconnected to the first lower wire LWL1 through a bridge line BWL. Athird scan line SL3 connected to a pixel circuit PC may be connected tothe second upper wire UWL2 through a bridge line BWL. A thirdlight-emission control line EL3 connected to a pixel circuit PC may beconnected to the fourth lower wire LWL4. Thus, when three pixel circuitsPC are arranged on the strip portion STP, a total of six second cornerwires CWLb may be used. In this way, when N (where N is an odd number)pixel circuits PC are arranged on the strip portion STP, a total of(N+1) ×1.5 second corner wires CWLb may be used. Because the secondcorner wire CWLb is connected to two of the plurality of pixel circuitsPC as described above, the number of wires arranged on the strip portionSTP may be minimized or reduced.

Referring to FIG. 12D, four pixel circuits PC may be arranged on thestrip portion STP. In this case, the second corner wire CWLb may includea first lower wire LWL1, a second lower wire LWL2, a third lower wireLWL3, a fourth lower wire LWL4, a first upper wire UWL1, a second upperwire UWL2, and a third upper wire UWL3. In an embodiment, the firstlower wire LWL1, the second lower wire LWL2, and the first upper wireUWL1 may be arranged in the first outer area OA1. The third lower wireLWL3, the fourth lower wire LWL4, the second upper wire UWL2, and thethird upper wire UWL3 may be arranged in the second outer area OA2.

In the illustrated embodiment, the fourth lower wire LWL4, the secondupper wire UWL2, the third lower wire LWL3, and the third upper wireUWL3 may be sequentially arranged in the first vertical direction VDR1.

In the illustrated embodiment, the second corner wire CWLb may beconnected to two of the plurality of pixel circuits PC. In detail, aprevious scan line and a current scan line connected to adjacent pixelcircuits PC may be connected to the same second corner wire CWLb. In anembodiment, a first scan line SL1 and a second previous scan line SL2-1connected to pixel circuits PC may be connected to the first upper wireUWL1 through bridge lines BWL, for example. A second scan line SL2 and athird previous scan line SL3-1 connected to pixel circuits PC may beconnected to the third lower wire LWL3 through bridge lines BWL. A thirdscan line SL3 and a fourth previous scan line SL4-1 connected to pixelcircuits PC may be connected to the second upper wire UWL2 throughbridge lines BWL.

In an embodiment, light-emission control lines connected to adjacentpixel circuits PC may be connected to the same second corner wire CWLb.In an embodiment, a first light-emission control line EL1 and a secondlight-emission control line EL2 connected to adjacent pixel circuits PCmay be connected to the second lower wire LWL2 through bridge lines BWL,for example. A third light-emission control line EL3 and a fourthlight-emission control line EL4 connected to adjacent pixel circuits PCmay be connected to the fourth lower wire LWL4 through bridge lines BWL.

A first previous scan line SL1-1 connected to a pixel circuit PC may beconnected to the first lower wire LWL1 through a bridge line BWL. Afourth scan line SL4 connected to a pixel circuit PC may be connected tothe third upper wire UWL3 through a bridge line BWL. Thus, when fourpixel circuits PC are arranged on the strip portion STP, a total ofseven second corner wires CWLb may be used. In this way, when N (where Nis an even number) pixel circuits PC are arranged on the strip portionSTP, a total of 1.5xN+1 second corner wires CWLb may be used. Becausethe second corner wire CWLb is connected to two of the plurality ofpixel circuits PC as described above, the number of wires arranged onthe strip portion STP may be minimized or reduced.

FIG. 12E is a cross-sectional view of a pixel circuit PC of FIG. 12Ctaken along line VIII-VIII′. Reference numerals in FIG. 12E that are thesame as the reference numerals in FIGS. 3DA and 12C denote the sameelements, and thus repeated descriptions thereof are omitted.

Referring to FIG. 12E, the display panel may include the substrate 100,a buffer layer 111, a pixel circuit layer PCL, a display element layerDEL, and a thin-film encapsulation layer TFE.

The substrate 100 may include a corner display area, the corner displayarea may include a plurality of strip portions, and spaces V may bedefined between the plurality of strip portions. Each of the pluralityof strip portions STP may include a center area CA, and a first outerarea OA1 and a second outer area OA2 arranged on both sides of thecenter area CA.

The buffer layer 111, the pixel circuit layer PCL, the display elementlayer DEL, and the thin-film encapsulation layer TFE may be stacked onthe substrate 100. The pixel circuit layer PCL may include the inorganicinsulating layer IIL, the first corner wire CWLa, the second corner wireCWLb, the pixel circuit PC, the first planarization layer 115, and thesecond planarization layer 116. The inorganic insulating layer IIL mayinclude the first gate insulating layer 112, the second gate insulatinglayer 113, and the interlayer insulating layer 114.

The first corner wire CWLa may include a first data line DL1′, a seconddata line DL2′, and a third data line DL3′. The second corner wire CWLbmay include a first lower wire LWL1, a second lower wire LWL2, a thirdlower wire LWL3, a fourth lower wire LWL4, a first upper wire UWL1, anda second upper wire UWL2.

The display element layer DEL may include a second red subpixel Pr2, asecond green subpixel Pg2, and a second blue subpixel Pb2. Each of thesecond red subpixel Pr2, the second green subpixel Pg2, and the secondblue supixel Pb2 may include the second display element DE2 (refer toFIG. 12A). The second display element DE2 may be an organiclight-emitting diode OLED. In an embodiment, the second red subpixel Pr2may be connected to a first subpixel circuit PCa, the second greensubpixel Pg2 may be connected to a second subpixel circuit PCb, and thesecond blue subpixel Pb2 may be connected to a third subpixel circuitPCc. The thin-film encapsulation layer TFE may include a first inorganicencapsulation layer 310, an organic encapsulation layer 320, and asecond inorganic encapsulation layer 330.

A semiconductor layer of the first subpixel circuit PCa, a semiconductorlayer of the second subpixel circuit PCb, and a semiconductor layer ofthe third subpixel circuit PCc may be arranged on the buffer layer 111.The first gate insulating layer 112 may cover the semiconductor layers.

The first previous scan line SL1-1, the first lower wire LWL1, thesecond lower wire LWL2, the third lower wire LWL3, and the fourth lowerwire LWL4 may be arranged on the first gate insulating layer 112. Thefirst lower wire LWL1 and the second lower wire LWL2 may be on the firstouter area OA1, and the third lower wire LWL3 and the fourth lower wireLWL4 may be on the second outer area OA2. In an embodiment, at least oneof the first previous scan line SL1-1, the first lower wire LWL1, thesecond lower wire LWL2, the third lower wire LWL3, and the fourth lowerwire LWL4 may include a conductive material including at least one ofmolybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and maybe a multi-layer or single layer including the aforementioned materials,for example. In an embodiment, at least one of the first previous scanline SL1-1, the first lower wire LWL1, the second lower wire LWL2, thethird lower wire LWL3, and the fourth lower wire LWL4 may be providedsimultaneously with forming of the gate electrode G of FIG. 3DA.

The second gate insulating layer 113 may cover the first lower wireLWL1, the second lower wire LWL2, the third lower wire LWL3, and thefourth lower wire LWL4. The first upper wire UWL1 and the second upperwire UWL2 may be on the second gate insulating layer 113. The firstlower wire LWL1, the first upper wire UWL1, and the second lower wireLWL2 may be sequentially arranged in a direction from the center area CAto the first outer area OA1. At least one of the first upper wire UWL1and the second upper wire UWL2 may include aluminum (Al), platinum (Pt),palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni),neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum(Mo), titanium (Ti), tungsten (W), and copper (Cu), and may each be asingle layer or multi-layer including the aforementioned materials. Atleast one of the first upper wire UWL1 and the second upper wire UWL2may be provided simultaneously with forming of the upper electrode CE2of FIG. 3DA.

In this case, the first upper wire UWL1 is arranged in a different layerfrom the layer in which the first lower wire LWL1 and the second lowerwire LWL2 are arranged, thereby reducing the width of the first outerarea OA1. Similarly, the third lower wire LWL3, the second upper wireUWL2, and the fourth lower wire LWL4 may be sequentially arranged in adirection from the center area CA to the second outer area OA2. In thiscase, the third lower wire LWL3 and the fourth lower wire LWL4 arearranged in a different layer from the layer in which the second upperwire UWL2 is arranged, thereby reducing the width of the second outerarea OA2.

The interlayer insulating layer 114 may cover the first upper wire UWL1and the second upper wire UWL2. The first data line DL1′, the seconddata line DL2′, the third data line DL3′, and the bridge line BWL may beon the interlayer insulating layer 114. The first data line DL1′, thesecond data line DL2′, and the third data line DL3′ may be connected tothe first subpixel circuit PCa, the second subpixel circuit PCb, and thethird subpixel circuit PCc, respectively. Accordingly, data signals maybe transmitted to the first subpixel circuit PCa, the second subpixelcircuit PCb, and the third subpixel circuit PCc, respectively.

The second gate insulating layer 113 and the interlayer insulating layer114 may include a first contact hole CNT1 and a second contact holeCNT2. The first contact hole CNT1 may expose the first lower wire LWL1,and the second contact hole CNT2 may expose the first previous scan lineSL1-1.

The bridge line BWL may extend from at least one of the first outer areaOA1 and the second outer area OA2 to the center area CA. The bridge lineBWL may be connected to the first lower wire LWL1 and the first previousscan line SL1-1 through the first contact hole CNT1 and the secondcontact hole CNT2, respectively.

In an embodiment, at least one of the first data line DL1′, the seconddata line DL2′, the third data line DL3′, and the bridge line BWL mayinclude a conductive material including at least one of molybdenum (Mo),aluminum (Al), copper (Cu), and titanium (Ti), and may be a multi-layeror single layer including the aforementioned materials, for example. Atleast one of the first data line DL1′, the second data line DL2′, thethird data line DL3′, and the bridge line BWL may have a multi-layerstructure of Ti/Al/Ti. At least one of the first data line DL1′, thesecond data line DL2′, the third data line DL3′, and the bridge line BWLmay be provided simultaneously with forming of the drain electrode D andthe source electrode S of FIG. 3DA.

As shown in FIG. 12E, a first scan line and a first light-emissioncontrol line may be connected to the first subpixel circuit PCa, thesecond subpixel circuit PCb, and the third subpixel circuit PCc. Thefirst scan line and the first light-emission control line may transmit ascan signal and a light-emission control signal to the first subpixelcircuit PCa, the second subpixel circuit PCb, and the third subpixelcircuit PCc. The first upper wire UWL1 may be connected to the firstscan line and may transmit the scan signal to the pixel circuit PC.Similarly, the second lower wire LWL2 may be connected to the firstlight-emission control line and may transmit the light-emission controlsignal to the pixel circuit PC. Accordingly, in an embodiment, even whenthe space V is defined between adjacent strip portions, a signal may betransmitted to the pixel circuit PC.

The first planarization layer 115 may be arranged on the first cornerwire CWLa and the bridge line BWL, and a connecting electrode CML and anupper connection line UCWL may be arranged on the first planarizationlayer 115. The connecting electrode CML may connect the pixel circuit PCto a second display element DE2. Similar to the first corner wire CWLaand/or the second corner wire CWLb, the upper connection line UCWL mayextend from a middle display area to a corner display area. In detail,the upper connection line UCWL may extend in the first extensiondirection EDR1 of FIG. 12C. The upper connection line UCWL may transmitthe initializing voltage Vint of FIG. 7, the driving voltage ELVDD ofFIG. 7, or/and the common voltage ELVSS of FIG. 7 to the pixel circuitPC. In an embodiment, the upper connection line UCWL may be between theinterlayer insulating layer 114 and the first planarization layer 115.

The upper connection line UCWL may include a conductive materialincluding molybdenum (Mo), aluminum (Al), copper (Cu), and titanium(Ti), and may be a multi-layer or single layer including theaforementioned materials. In an embodiment, the upper connection lineUCWL may have a multi-layer structure of Ti/Al/Ti.

The first inorganic pattern layer PVX1 may be on the first planarizationlayer 115 and/or the upper connection line UCWL. A plurality of firstinorganic pattern layers PVX1 may be arranged on the upper connectionline UCWL, and the plurality of first inorganic pattern layers PVX1 maybe spaced apart from each other on the upper connection line UCWL.

The second planarization layer 116 may cover the upper connection lineUCWL, the connecting electrode CML, and the first planarization layer115. In an embodiment, a groove Gv may be defined in the secondplanarization layer 116. The second planarization layer 116 may includea hole H, and the hole H may correspond to the first inorganic patternlayer PVX1. The second planarization layer 116 may cover the edge of thefirst inorganic pattern layer PVX1. Accordingly, the groove Gv may bedefined by a center portion of the first inorganic pattern layer PVX1and the hole H of the second planarization layer 116. When the organicencapsulation layer 320 is provided, the groove Gv may control flow ofan organic material that forms the organic encapsulation layer 320.

A second inorganic pattern layer PVX2 and the second display element DE2may be on the second planarization layer 116. Second inorganic patternlayers PVX2 may be on both sides of the groove Gv, and may include apair of protruding tips protruding in a center direction of the grooveGv.

A first functional layer 212 a, a second functional layer 212 c, and anopposite electrode 213 arranged on the second inorganic pattern layerPVX2 may be disconnected by the groove Gv and the pair of protrudingtips. In an embodiment, a first functional layer pattern, a secondfunctional layer pattern, and an opposite electrode pattern may bearranged within the groove Gv.

A dam unit DP and an auxiliary dam unit ADP protruding in a thicknessdirection of the substrate 100 may be above the second inorganic patternlayer PVX2. The auxiliary dam unit ADP may be between the dam unit DPand the second display element DE2.

In an embodiment, the groove Gv may be between the dam unit DP and theauxiliary dam unit ADP, and the groove Gv may also be between theauxiliary dam unit ADP and the second display element DE2.

In an embodiment, a height between the upper surface of the substrate100 to the upper surface of the dam unit DP may be greater than a heightbetween the upper surface of the substrate 100 and the upper surface ofthe auxiliary dam unit ADP.

In an embodiment, the first inorganic encapsulation layer 310 mayentirely and consecutively cover the strip portion STP. In detail, thefirst inorganic encapsulation layer 310 may entirely and consecutivelycover the dam unit DP, the auxiliary dam unit ADP, the groove Gv, andthe second display element DE2. In this case, the first inorganicencapsulation layer 310 may contact the second inorganic pattern layerPVX2. The organic encapsulation layer 320 may extend from the seconddisplay element DE2 to the dam unit DP. The organic encapsulation layer320 may fill the groove Gv. Similar to the first inorganic encapsulationlayer 310, the second inorganic encapsulation layer 330 may entirely andconsecutively cover the strip portion STP. In an embodiment, the secondinorganic encapsulation layer 330 may contact the first inorganicencapsulation layer 310 in the dam unit DP.

Although only a display panel and a display apparatus have been focusedon and described above, the invention is not limited thereto. A methodof manufacturing the display panel, for example, and a method ofmanufacturing the display apparatus may belong to the scope of theinvention.

In an embodiment, a display panel and a display apparatus in which adisplay area is expanded may be realized. Of course, the scope of theinvention is not limited thereto.

It should be understood that embodiments described herein should beconsidered in a descriptive sense only and not for purposes oflimitation. Descriptions of features or advantages within eachembodiment should typically be considered as available for other similarfeatures or advantages in other embodiments. While one or moreembodiments have been described with reference to the drawing figures,it will be understood by those of ordinary skill in the art that variouschanges in form and details may be made therein without departing fromthe spirit and scope as defined by the following claims.

What is claimed is:
 1. A display panel comprising: a substratecomprising a display area and a peripheral area around the display area,the display area comprising a front display area, a corner display areaextending from a corner of the front display area, and a middle displayarea between the front display area and the corner display area; a pixelarranged on the front display area and comprising a display element; agate driving circuit arranged on a side of the peripheral area; a datadriving circuit arranged on the side on which the gate driving circuitis arranged; a gate line connected to the gate driving circuit andextending in a first direction to be connected to the pixel; and a dataline connected to the data driving circuit and extending in a seconddirection intersecting the first direction to be connected to the pixel.2. The display panel of claim 1, further comprising a gate connectionline extending in the second direction and including a first sideconnected to the gate driving circuit and a second side connected to thegate line.
 3. The display panel of claim 1, further comprising a dataconnection line including a first side connected to the data drivingcircuit and a second side connected to the data line adjacent to theedge of the front display area.
 4. The display panel of claim 3, whereinthe data connection line at least partially overlaps the front displayarea.
 5. The display panel of claim 4, further comprising: a voltagewire arranged on the substrate to correspond to the middle display area;a middle display element arranged to at least partially overlap thevoltage wire; and a middle pixel circuit which is connected to themiddle display element and drives the middle display element, whereinthe middle pixel circuit is arranged in the front display area.
 6. Thedisplay panel of claim 5, wherein a light-emission area of the displayelement is smaller than a light-emission area of the middle displayelement.
 7. The display panel of claim 4, further comprising: a cornerdisplay element arranged on the substrate to correspond to the cornerdisplay area; and a corner pixel circuit which is connected to thecorner display element and drives the corner display element, whereinthe corner pixel circuit is arranged in the front display area or thecorner display area.
 8. The display panel of claim 7, wherein alight-emission area of the display element is smaller than alight-emission area of the corner display element.
 9. The display panelof claim 7, further comprising: a first corner wire arranged in thecorner display area and connected to the data line; and a second cornerwire arranged in the corner display area and connected to the gate line,wherein the first corner wire and the second corner wire are connectedto the corner pixel circuit.
 10. The display panel of claim 9, whereinthe substrate corresponding to the corner display area comprises: aplurality of strip portions each extending in a direction away from thefront display area; and a plurality of spaces each defined betweenadjacent strip portions from among the plurality of strip portions, andpenetrating through the substrate, wherein the first corner wire and thesecond corner wire are arranged in each of the plurality of stripportions.
 11. The display panel of claim 3, wherein the data connectionline at least partially overlaps the middle display area.
 12. Thedisplay panel of claim 11, further comprising: a middle display elementarranged to at least partially overlap the data connection line; and amiddle pixel circuit which is connected to the middle display elementand drives the middle display element, wherein the middle pixel circuitis arranged in the front display area.
 13. The display panel of claim11, further comprising: a corner display element arranged on thesubstrate to correspond to the corner display area; and a corner pixelcircuit which is connected to the corner display element and drives thecorner display element, wherein the corner pixel circuit is arranged inthe front display area or the corner display area.
 14. The display panelof claim 1, further comprising: a first voltage wire and a secondvoltage wire arranged in the peripheral area and spaced apart from eachother with the middle display area between the first voltage wire andthe second voltage wire; and a voltage connection line arranged in thecorner display area and connecting the first voltage wire to the secondvoltage wire.
 15. The display panel of claim 14, wherein the substratecorresponding to the corner display area comprises: a plurality of stripportions each extending in a direction away from the front display area;and a plurality of spaces each defined between adjacent strip portionsfrom among the plurality of strip portions, and penetrating through thesubstrate, wherein the voltage connection line is arranged along theedges of the plurality of strip portions.
 16. The display panel of claim14, further comprising: a corner display element arranged on thesubstrate to correspond to the corner display area; and a corner pixelcircuit which is connected to the corner display element and drives thecorner display element, wherein the corner pixel circuit is arranged inthe front display area or the corner display area.
 17. The display panelof claim 14, further comprising: a middle display element arranged onthe substrate to correspond to the middle display area; and a middlepixel circuit which is connected to the middle display element anddrives the middle display element, wherein the middle pixel circuit isarranged in the front display area or the middle display area.
 18. Adisplay apparatus comprising: a display panel including: a substratewhich comprises: a display area and a peripheral area around the displayarea, the display area comprising a front display area, a corner displayarea extending from a corner of the front display area and bent with apreset radius of curvature; and a middle display area between the frontdisplay area and the corner display area; a pixel arranged on the frontdisplay area and comprising a display element; a gate driving circuitarranged on a side of the peripheral area; a data driving circuitarranged on the side on which the gate driving circuit is arranged; agate line connected to the gate driving circuit and extending in a firstdirection to be connected to the pixel; and a data line connected to thedata driving circuit and extending in a second direction intersectingthe first direction to be connected to the pixel; and a window coveringthe display panel.
 19. The display apparatus of claim 18, wherein thedisplay panel further comprises: a gate connection line extending in thesecond direction and including a first side connected to the gatedriving circuit and a second side connected to the gate line; and a dataconnection line including a first side connected to the data drivingcircuit and a second side connected to the data line, and the dataconnection line at least partially overlaps the front display area orthe middle display area.
 20. The display apparatus of claim 18, whereinthe display panel further comprises: a voltage wire arranged on thesubstrate to correspond to the middle display area; a middle displayelement arranged to at least partially overlap the voltage wire; and amiddle pixel circuit which is connected to the middle display elementand drives the middle display element, wherein the middle pixel circuitis arranged in the front display area.
 21. The display apparatus ofclaim 18, wherein the display panel further comprises: a corner displayelement arranged on the substrate to correspond to the corner displayarea; and a corner pixel circuit which is connected to the cornerdisplay element and drives the corner display element, wherein thecorner pixel circuit is arranged in the front display area or the cornerdisplay area.